Toshiyuki Shibuya

19 papers A* 1A 3C 1Journal 5Unranked 8

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Conference Reports: Recap of the 24th Asia and South Pacific Design Automation Conference. IEEE Des. Test Toshiyuki Shibuya
2019	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshiyuki Shibuya
2019	—	`ed.`	Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019 ASPDAC Toshiyuki Shibuya
2013	—	`conf`	A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. ISSCC Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada
2011	—	`conf`	A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. ISSCC Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker
2011	J	`jnl`	A New Strategy for Simultaneous Escape Based on Boundary Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya
2010	—	`conf`	"Condition-based" dummy fill insertion method based on ECP and CMP predictive models. ISQED Izumi Nitta, Yuji Kanazawa, Daisuke Fukuda, Toshiyuki Shibuya, Naoki Idani, Masaru Ito, Osamu Yamasaki, Norihiro Harada, Takanori Hiramoto
2010	—	`conf`	B-escape: a simultaneous escape routing algorithm based on boundary routing. ISPD Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya
2010	A*	`conf`	Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances. DAC Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa
2009	J	`jnl`	Efficient Power Network Analysis Considering Multidomain Clock Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng
2009	—	`conf`	Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit. ASP-DAC Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya
2009	J	`jnl`	Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya
2008	A	`conf`	Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. DATE Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng
2008	—	`conf`	Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis. ASP-DAC Katsumi Homma, Izumi Nitta, Toshiyuki Shibuya
2007	C	`conf`	Fast power network analysis with multiple clock domains. ICCD Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng
2005	—	`conf`	Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
2003	—	`conf`	PDL: A New Physical Synthesis Methodology. ISQED Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura
1997	A	`conf`	Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. ICCAD Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu
1990	A	`conf`	Touch and Cross Router. ICCAD Kaoru Kawamura, Tatsuya Shindo, Toshiyuki Shibuya, Hideki Miwatari, Yoshie Ohki