Toshiro Tsukada

14 papers Journal 11Unranked 3
YearRankTypeTitle / Venue / Authors
2009 J jnl
Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation.
IEICE Trans. Electron.
Masataka Miyake, Daisuke Hori, Norio Sadachika, Uwe Feldmann, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Takahiro Iizuka, Kazuya Matsuzawa, Yasuyuki Sahara, Teruhiko Hoshida, Toshiro Tsukada
2008 J jnl
Special Section on Analog Circuit Techniques and Related Topics.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Toshiro Tsukada
2007 J jnl
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm.
IEICE Trans. Electron.
Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada
2006 J jnl
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada
2006 J jnl
High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masafumi Uemori, Haruo Kobayashi, Tomonari Ichikawa, Atsushi Wada, Koichiro Mashiko, Toshiro Tsukada, Masao Hotta
2006 J jnl
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.
IEICE Trans. Electron.
Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada
2005 J jnl
An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs.
IEEE J. Solid State Circuits
Toshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, Koichiro Ishibashi
2005 — conf
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias.
CICC
Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata
2003 — conf
Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technology.
ESSCIRC
Hiroyuki Okada, Yasuyuki Hashimoto, Kohji Sakata, Toshiro Tsukada, Koichiro Ishibashi
1999 J jnl
Substrate noise measurement by using noise-selective voltage comparators in analog and digital mixed-signal integrated circuits.
IEEE Trans. Instrum. Meas.
Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada
1998 — conf
A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling.
ASP-DAC
Seiji Funaba, Akihiro Kitagawa, Toshiro Tsukada, Goichi Yokomizo
1996 J jnl
Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor.
IEEE J. Solid State Circuits
Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta
1996 J jnl
Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits.
IEEE J. Solid State Circuits
Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta
1980 J jnl
An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter.
IEEE Trans. Computers
Tsuneo Funabashi, Katsuaki Takagi, Toshiro Tsukada, Hideo Nakamura, Michio Hara