Toshiro Hiramoto

35 papers A 3C 1Journal 13Unranked 18

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Study on the Origin of MOSFET Random Telegraph Noise Under Strong Inversion at Cryogenic Temperatures. IRPS Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hiroshi Oka, Takahiro Mori, Shinichi Takagi, Masaharu Kobayashi, Toshiro Hiramoto
2024	—	`conf`	Performance and Reliability of Nanosheet Oxide Semiconductor FETs with ALD-Grown InGaO for 3D Integration (Invited). IRPS Masaharu Kobayashi, Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka
2024	—	`conf`	Scaling Potential of Nanosheet Oxide Semiconductor FETs for Monolithic 3D Integration-ALD Material Engineering, High-Field Transport, Statistical Variability. VLSI Technology and Circuits Kaito Hikake, Xingyu Huang, Sung-Hun Kim, Kota Sakai, Zhuo Li, Tomoko Mizutani, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi
2023	—	`conf`	A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices. VLSI Technology and Circuits Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi
2022	—	`conf`	3-Layer stacked pixel-parallel CMOS image sensors using hybrid bonding of SOI wafers. Imaging Sensors and Systems Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
2021	—	`conf`	Recent Progress of Double/Dual-Gate Silicon IGBT Technologies. ASICON Toshiro Hiramoto, Takuya Saraya
2020	—	`conf`	An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. AICAS Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto
2019	—	`conf`	Comprehensive Understanding of Negative Capacitance FET From the Perspective of Transient Ferroelectric Model. ASICON Masaharu Kobayashi, Chengji Jin, Toshiro Hiramoto
2019	—	`conf`	Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method. NVMTS Fei Mo, Yusaku Tagawa, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi
2019	—	`conf`	Switching of 3300V Scaled IGBT by 5V Gate Drive. ASICON Toshiro Hiramoto, Katsumi Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Naoyuki Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, Hiromichi Ohashi, Kazuo Itou, Toshihiro Takakura, Munetoshi Fukui, Shinichi Suzuki, Ken Takeuchi, Masanori Tsukuda, Yohichiroh Numasawa
2019	—	`conf`	Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers. 3DIC Masahide Goto, Joeri De Vos, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Eiji Higurashi, Yuki Honda, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
2018	—	`conf`	New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. VLSI Circuits Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai
2018	C	`conf`	Quarter Video Graphics Array Full-Digital Image Sensing with Wide Dynamic Range and Linear Output Using Pixel-Wise 3D Integration. ISCAS Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
2018	—	`conf`	Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately. ESSDERC Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai
2017	—	`conf`	3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). ASICON Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, Masaharu Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura, Y. Numasawa, Ichiro Omura, Hiromichi Ohashi, Hiroshi Iwai
2017	—	`conf`	Parallel nonvolatile programming of power-up states of SRAM cells. ASICON Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi
2015	J	`jnl`	Nanoelectronics Research Gaps and Recommendations: A Report from the International Planning Working Group on Nanoelectronics (IPWGN) [Commentary]. IEEE Technol. Soc. Mag. Kosmas Galatsis, Paolo Gargini, Toshiro Hiramoto, Dirk Beernaert, Roger DeKeersmaecker, Joachim Pelka, Lothar Pfitzner
2015	—	`conf`	Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers. 3DIC Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
2013	J	`jnl`	Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress. IEICE Trans. Electron. Toshiro Hiramoto, Anil Kumar, Takuya Saraya, Shinji Miyano
2013	J	`jnl`	NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM. IEICE Trans. Electron. Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, Toshiro Hiramoto
2013	J	`jnl`	Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs. IEICE Trans. Electron. Tomoko Mizutani, Anil Kumar, Toshiro Hiramoto
2011	—	`conf`	Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs. CICC Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, Takuya Saraya
2011	A	`conf`	Ultra-low-voltage operation: device perspective. ISLPED Toshiro Hiramoto
2010	J	`jnl`	Nanoelectronics Research for Beyond CMOS Information Processing. Proc. IEEE George Bourianoff, Michel Brillouët, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida
2010	J	`jnl`	Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps. Proc. IEEE Michel Brillouët, George Bourianoff, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida
2007	J	`jnl`	Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations. IEICE Trans. Electron. Toshiro Hiramoto, Toshiharu Nagumo, Tetsu Ohtou, Kouki Yokoyama
2006	J	`jnl`	Emerging nanoscale silicon devices taking advantage of nanostructure physics. IBM J. Res. Dev. Toshiro Hiramoto, Masumi Saitoh, Gen Tsutsui
2003	J	`jnl`	VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. IEEE Trans. Very Large Scale Integr. Syst. Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai
2001	A	`conf`	VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. ISLPED Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai
2001	A	`conf`	Variable threshold CMOS (VTCMOS) in series connected circuits. ISLPED Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai
2000	—	`conf`	Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration. CICC Takashi Inukai, Makoto Takamiya, Kouichi Nose, Hiroshi Kawaguchi, Toshiro Hiramoto, Takayasu Sakurai
1994	J	`jnl`	A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates. IEEE J. Solid State Circuits Nobuo Tamba, Akio Anzai, Kazuhiro Akimoto, Masayuki Ohayashi, Toshiro Hiramoto, Tadanori Kokubu, Sohei Ohmori, Tetsuya Muraya, Atsuyuki Kishimoto, Sousuke Tsuji, Hideki Hayashi, Nadateru Handa, Toshio Igarashi, Hiroaki Nambu, Makoto Yoshida, Tsuyoshi Fujiwara, Kunihiko Watanabe, Akihisa Uchida, Masanori Odaka, Kunihiko Yamaguchi, Takahide Ikeda
1994	J	`jnl`	A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. IEEE J. Solid State Circuits Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima
1992	J	`jnl`	A 1.5-ns access time, 78- mu m IEEE J. Solid State Circuits Kunihiko Yamaguchi, Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Toshiro Hiramoto, Nobuo Tamba, Kunihiko Watanabe, Masanori Odaka, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai
1992	J	`jnl`	High-speed sensing techniques for ultrahigh-speed SRAMs. IEEE J. Solid State Circuits Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Kunihiko Yamaguchi, Toshiro Hiramoto, Nobuo Tamba, Masanori Odaka, Kunihiko Watanabe, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai