Toshio Yamada

21 papers A* 4B 1Journal 11Unranked 5
YearRankTypeTitle / Venue / Authors
2013 J jnl
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation.
IEICE Trans. Electron.
Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2012 J jnl
On-Chip In-Place Measurements of V
IEICE Trans. Electron.
Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011 J jnl
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits.
IEICE Trans. Electron.
Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011 — conf
Accurate analysis of substrate sensitivity of active transistors in an analog circuit.
ISQED
Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011 J jnl
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement.
IEICE Trans. Electron.
Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2004 A* conf
MVL Toolkit: Software Library for Constructing an Immersive Shared Virtual World.
VR
Tetsuro Ogi, Takuro Kayahara, Toshio Yamada, Michitaka Hirose
2003 A* conf
High Presence Remote Presentation in the Shared Immersive Virtual World.
VR
Tetsuro Ogi, Toshio Yamada, Michitaka Hirose, Masahiro Fujita, Kazuto Kuzuu
2002 A* conf
Desk-Sized Immersive Workplace Using Force Feedback Grid Interface.
VR
Toshio Yamada, Daisuke Tsubouchi, Tetsuro Ogi, Michitaka Hirose
2001 J jnl
Developing a 2.5-D video avatar.
IEEE Signal Process. Mag.
Ken Tamagawa, Toshio Yamada, Tetsuro Ogi, Michitaka Hirose
2001 — conf
Experience of Immersive Virtual World Using Cellular Phone Interface.
IEEE Pacific Rim Conference on Multimedia
Tetsuro Ogi, Koji Yamamoto, Toshio Yamada, Michitaka Hirose
2001 A* conf
Immersive Telecommunication Using Stereo Video Avatar.
VR
Tetsuro Ogi, Toshio Yamada, Ken Tamagawa, Makoto Kano, Michitaka Hirose
2001 — conf
Invisible Interface for the Immersive Virtual World.
EGVE/IPT
Tetsuro Ogi, Toshio Yamada, Koji Yamamoto, Michitaka Hirose
2001 B conf
Multimedia Virtual Laboratory.
INTERACT
Tetsuro Ogi, Toshio Yamada, Koichi Hirota, Michitaka Hirose
2000 J jnl
An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D
IEEE J. Solid State Circuits
Yasuhiro Agata, Kenji Motomochi, Yoshifumi Fukushima, Masanori Shirahama, Marefusa Kurumada, Naoki Kuroda, Hiroyuki Sadakata, Kohtaro Hayashi, Toshio Yamada, Kazunari Takahashi, Tsutomu Fujita
1999 — conf
CABINet: networking of immersive projection environment.
HCI (2)
Tetsuro Ogi, Toshio Yamada, Michitaka Hirose
1999 J jnl
Development and evaluation of the CABIN immersive multiscreen display.
Syst. Comput. Jpn.
Michitaka Hirose, Tetsuro Ogi, Shohei Ishiwata, Toshio Yamada
1999 — conf
Development of Stereo Video Avatar in Networked Immersive Projection Environment.
ICIP (3)
Michitaka Hirose, Tetsuro Ogi, Toshio Yamada, Ken Tamagawa
1999 J jnl
Integrating Live Video for Immersive Environments.
IEEE Multim.
Michitaka Hirose, Tetsuro Ogi, Toshio Yamada
1993 J jnl
A New Testing Acceleration Chip for Low-Cost Memory Tests.
IEEE Des. Test Comput.
Michihiro Inoue, Toshio Yamada, Atsushi Fujiwara
1991 J jnl
A 64-Mb DRAM with meshed power line.
IEEE J. Solid State Circuits
Toshio Yamada, Yoshiro Nakata, Junko Hasegawa, Noriaki Amano, Akinori Shibayama, Masaru Sasago, Naoto Matsuo, Toshiki Yabu, Susumu Matsumoto, Shozo Okada, Michihiro Inoue
1988 J jnl
A 4-Mbit DRAM with 16-bit concurrent ECC.
IEEE J. Solid State Circuits
Toshio Yamada, Hisakazu Kotani, Junko Matsushima, Michihiro Inoue