Toshinori Sato

115 papers A 1B 4C 15Misc 5Journal 30Unranked 59
YearRankTypeTitle / Venue / Authors
2025 — conf
Approximate Logarithmic Squarers for QRS Identification on Arrhythmia Detection and Classification.
ICDSP
Toshinori Sato, Taiki Nagatomo
2025 J jnl
Teleradiology-Based Referrals for Patients with Gastroenterological Diseases Between Tertiary and Regional Hospitals: A Hospital-to-Hospital Approach.
J. Imaging Inform. Medicine
Kosuke Suzuki, Hiroaki Saito, Yoshika Saito, Akashi Endo, Daichi Togo, Risa Hanada, Rie Iwaya, Toshinori Sato, Kei Niida, Ryuta Suzuki, Junichi Togashi, Satoshi Ito, Yukari Tanaka, Yoshitaka Nawata, Kimihiro Igarashi, Hidetaka Hamamoto, Akihiko Ozaki, Tetsuya Tanimoto, Yasuteru Shimamura, Shunichi Sugawara, Masaki Nakashima, Toru Okuzono, Masato Nakahori, Akimichi Chonan, Tomoki Matsuda
2024 C conf
A Light-weight and Tamper-resistant AES Implementation by FPGAs.
ISCAS
Yui Koyanagi, Tomoaki Ukezono, Toshinori Sato
2024 — conf
Cost-effective Alternatives for Squarer in Pan-Tompkins Algorithm.
IECC
Taiki Nagatomo, Toshinori Sato
2024 — conf
Dialogue Systems Can Generate Appropriate Responses without the Use of Question Marks?- a Study of the Effects of "?" for Spoken Dialogue Systems -.
LREC/COLING
Tomoya Mizumoto, Takato Yamazaki, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato
2024 — conf
Impact of Approximate QRS Identification on RR Interval-Based Arrhythmia Detection and Classification.
CISP-BMEI
Taiki Nagatomo, Toshinori Sato
2023 C conf
A Follow-up Study on Evaluation Metrics Using Follow-up Utterances.
PACLIC
Toshiki Kawamoto, Yuki Okano, Takato Yamazaki, Toshinori Sato, Kotaro Funakoshi, Manabu Okumura
2023 B conf
An Open-Domain Avatar Chatbot by Exploiting a Large Language Model.
SIGDIAL
Takato Yamazaki, Tomoya Mizumoto, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato
2023 Misc conf
Bridging the Gap between Subword and Character Segmentation in Pretrained Language Models.
RANLP
Shun Kiyono, Sho Takase, Shengzhe Li, Toshinori Sato
2023 J jnl
Building a hospitable and reliable dialogue system for android robots: a scenario-based approach with large language models.
Adv. Robotics
Takato Yamazaki, Katsumasa Yoshikawa, Toshiki Kawamoto, Tomoya Mizumoto, Masaya Ohagi, Toshinori Sato
2023 — conf
Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition.
ISOCC
Toshinori Sato, Hiroyuki Hama, Tomoaki Ukezono
2023 J jnl
Dialogue Systems Can Generate Appropriate Responses without the Use of Question Marks? - Investigation of the Effects of Question Marks on Dialogue Systems.
CoRR
Tomoya Mizumoto, Takato Yamazaki, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato
2023 — conf
Leveraging Approximate Computing for IoT Image Transmission.
ISOCC
Hiroyuki Hama, Tomoaki Ukezono, Toshinori Sato
2023 — conf
Negative Impact of Approximated Signed Addition on Power Reduction.
ISDCS
Hiroyuki Hama, Tomoaki Ukezono, Toshinori Sato
2023 J jnl
PHALM: Building a Knowledge Graph from Scratch by Prompting Humans and a Language Model.
CoRR
Tatsuya Ide, Eiki Murata, Daisuke Kawahara, Takato Yamazaki, Shengzhe Li, Kenta Shinzato, Toshinori Sato
2023 — conf
Towards At-the-Edge ECG Signal Processing with Accuracy-tunable Approximate Adders.
GCCE
Hiroyuki Hama, Toshinori Sato
2022 — conf
An Accuracy-Controllable Approximate Adder for FPGAs.
ATAIT
Masaki Sano, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
2022 — conf
Building a Personalized Dialogue System with Prompt-Tuning.
NAACL-HLT (Student Research Workshop)
Tomohito Kasahara, Daisuke Kawahara, Nguyen Tung, Shengzhe Li, Kenta Shinzato, Toshinori Sato
2022 J jnl
Building a Personalized Dialogue System with Prompt-Tuning.
CoRR
Tomohito Kasahara, Daisuke Kawahara, Nguyen Tung, Shengzhe Li, Kenta Shinzato, Toshinori Sato
2022 — conf
Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge.
ACM Great Lakes Symposium on VLSI
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
2022 J jnl
Tourist Guidance Robot Based on HyperCLOVA.
CoRR
Takato Yamazaki, Katsumasa Yoshikawa, Toshiki Kawamoto, Masaya Ohagi, Tomoya Mizumoto, Shuta Ichimura, Yusuke Kida, Toshinori Sato
2020 — conf
A Dynamically Configurable Approximate Array Multiplier with Exact Mode.
ICCCS
Toshinori Sato, Tomoaki Ukezono
2020 J jnl
An Accuracy-Configurable Adder for Low-Power Applications.
IEICE Trans. Electron.
Tongxin Yang, Toshinori Sato, Tomoaki Ukezono
2020 J jnl
Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Toshinori Sato, Tomoaki Ukezono
2019 — conf
A Low-Power Approximate Multiply-Add Unit.
ISDCS
Tongxin Yang, Toshinori Sato, Tomoaki Ukezono
2019 — conf
An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area.
ISVLSI
Tongxin Yang, Toshinori Sato, Tomoaki Ukezono
2019 — conf
Correcting Sign Calculation Errors in Configurable Approximations.
APCCAS
Toshinori Sato, Tomoaki Ukezono
2019 J jnl
Design and Analysis of Approximate Multipliers with a Tree Compressor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
2019 — conf
Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method.
ACM Great Lakes Symposium on VLSI
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
2019 C conf
Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance.
PRDC
Toshinori Sato, Tomoaki Ukezono
2019 — conf
On Applications of Configurable Approximation to Irregular Voltage.
NORCAS
Toshinori Sato, Tomoaki Ukezono
2019 — conf
Tolerating Aging-Induced Timing Violations Via Configurable Approximations.
GCCE
Toshinori Sato, Tomoaki Ukezono
2019 J jnl
Trading Accuracy for Power with a Configurable Approximate Adder.
IEICE Trans. Electron.
Toshinori Sato, Tongxin Yang, Tomoaki Ukezono
2018 C conf
A Low-Power Yet High-Speed Configurable Adder for Approximate Computing.
ISCAS
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
2018 — conf
A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing.
ISVLSI
Hiroyuki Baba, Tongxin Yang, Masahiro Inoue, Kaori Tajima, Tomoaki Ukezono, Toshinori Sato
2018 — conf
A low-power configurable adder for approximate applications.
ISQED
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
2018 — conf
A low-power high-speed accuracy-controllable approximate multiplier design.
ASP-DAC
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
2018 — conf
Approximate Adder Generation for Image Processing Using Convolutional Neural Network.
ISOCC
Ryuta Ishida, Toshinori Sato, Tomoaki Ukezono
2018 J jnl
Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
2018 — conf
Exploiting Configurability for Correct Sign Calculation in an Approximate Adder.
ISOCC
Toshinori Sato, Tomoaki Ukezono
2017 C conf
Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor.
ICCD
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
2013 — conf
Improving timing error tolerance without impact on chip area and power consumption.
ISQED
Ken Yano, Takanori Hayashida, Toshinori Sato
2012 J jnl
A Selective Replacement Method for Timing-Error-Predicting flip-Flops.
J. Circuits Syst. Comput.
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida
2012 C conf
Analysis of SER Improvement by Radiation Hardened Latches.
PRDC
Ken Yano, Takanori Hayashida, Toshinori Sato
2012 — conf
Dynamically reducing overestimated design margin of MultiCores.
HPCS
Toshinori Sato, Takanori Hayashida, Ken Yano
2012 — conf
Guidelines for mitigating NBTI degradation in on-chip memories.
ISCIT
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida
2012 — conf
Importance of Single-Core Performance in the Multicore Era.
ACSC
Toshinori Sato, Hideki Mori, Rikiya Yano, Takanori Hayashida
2012 — conf
Topic 4: High-Performance Architecture and Compilers.
Euro-Par
Alex Veidenbaum, Nectarios Koziris, Toshinori Sato, Avi Mendelson
2011 Misc conf
Multicore Power Management Utilizing Error-Predicting Flip-flop.
CISIS
Toshinori Sato, Takahito Yoshiki, Takanori Hayashida
2011 J jnl
Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI.
IEICE Trans. Electron.
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
2010 C conf
A Replacement Strategy for Canary Flip-Flops.
PRDC
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
2010 — conf
Signal probability control for relieving NBTI in SRAM cells.
ISQED
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
2009 — conf
A case for exploiting complex arithmetic circuits towards performance yield enhancement.
ISQED
Shingo Watanabe, Masanori Hashimoto, Toshinori Sato
2009 J jnl
Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment.
IEICE Trans. Electron.
Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura
2009 — conf
Uncriticality-directed scheduling for tackling variation and power challenges.
ISQED
Toshinori Sato, Shingo Watanabe
2008 J jnl
A Low-Power Instruction Issue Queue for Microprocessors.
IEICE Trans. Electron.
Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato
2008 J jnl
A Simple Mechanism for Collapsing Instructions under Timing Speculation.
IEICE Trans. Electron.
Toshinori Sato
2008 — conf
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications.
SASP
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato
2008 — conf
Dependability, power, and performance trade-off on a multicore processor.
ASP-DAC
Toshinori Sato, Toshimasa Funaki
2008 C conf
Formulating MITF for a Multicore Processor with SEU Tolerance.
DSD
Toshimasa Funaki, Toshinori Sato
2008 — ed.
High-Performance Computing - 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers
ISHPC
Jesús Labarta, Kazuki Joe, Toshinori Sato
2008 — conf
Instruction Scheduling for Variation-Originated Variable Latencies.
ISQED
Toshinori Sato, Shingo Watanabe
2008 — conf
Uncriticality-Directed Low-Power Instruction Scheduling.
ISVLSI
Shingo Watanabe, Toshinori Sato
2007 — conf
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM.
ISQED
Toshinori Sato, Yuji Kunitake
2007 — conf
Challenges in Evaluations for a Typical-Case Design Methodology.
ISQED
Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato
2007 — conf
Exploiting Input Variations for Energy Reduction.
PATMOS
Toshinori Sato, Yuji Kunitake
2007 C conf
Indirect Tag Search Mechanism for Instruction Window Energy Reduction.
CIT
Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato
2007 J jnl
Introduction.
SIGARCH Comput. Archit. News
Kenji Kise, Toshinori Sato, Hironori Nakajo
2007 C conf
Power-Performance Trade-Off of a Dependable Multicore Processor.
PRDC
Toshinori Sato, Toshimasa Funaki
2007 J jnl
Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism.
Int. J. Comput. Their Appl.
Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu
2006 J jnl
A leakage-energy-reduction technique for cache memories in embedded processors.
J. Embed. Comput.
Seiichiri Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato
2006 J jnl
Energy-efficient instruction scheduling utilizing cache miss information.
SIGARCH Comput. Archit. News
Akihiro Chiyonobu, Toshinori Sato
2006 C conf
Evaluating the Impact of Fault Recovery on Superscalar Processor Performance.
PRDC
Toshinori Sato, Akihiro Chiyonobu
2006 — conf
Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors.
PATMOS
Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu
2005 J jnl
An Energy-Efficient Clustered Superscalar Processor.
IEICE Trans. Electron.
Toshinori Sato, Akihiro Chiyonobu
2005 Misc conf
Exploiting Trivial Computation in Dependable Processors.
CATA
Toshinori Sato
2005 — conf
Folding Active List for High Performance and Low Power.
ISHPC
Yuichiro Imaizumi, Toshinori Sato
2005 — conf
Profiling with Helper Threads.
Parallel and Distributed Computing and Networks
Takamasa Tokunaga, Toshinori Sato
2004 J jnl
A leakage-energy-reduction technique for highly-associative caches in embedded systems.
SIGARCH Comput. Archit. News
Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato
2004 — conf
A static and dynamic energy reduction technique for I-cache and BTB in embedded processors.
ASP-DAC
Hidenori Sato, Toshinori Sato
2004 — conf
Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture.
ISICT
Akihiro Chiyonobu, Toshinori Sato
2004 — conf
Leakage Energy Reduction in Register Renaming.
ICDCS Workshops
Masaharu Goto, Toshinori Sato
2004 C conf
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors.
EUC
Seiichiro Fujii, Toshinori Sato
2004 B conf
The potential in energy efficiency of a speculative chip-multiprocessor.
SPAA
Yuu Tanaka, Toshinori Sato, Takenori Koushiro
2003 — conf
A field-customizable and runtime-adaptable microarchitecture.
FPT
Toshinori Sato, Daisuke Morishita
2003 J jnl
A trace-level value predictor for Contrail processors.
SIGARCH Comput. Archit. News
Takenori Koushiro, Toshinori Sato, Itsujiro Arita
2003 J jnl
Combining variable latency pipeline with instruction reuse for execution latency reduction.
Syst. Comput. Jpn.
Toshinori Sato, Itsujiro Arita
2003 — conf
Exploiting Instruction Redundancy for Transient Fault Tolerance.
DFT
Toshinori Sato
2003 — conf
Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction.
PATMOS
Akihito Sakanaka, Toshinori Sato
2003 C conf
Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation.
CAINE
Asami Tanino, Toshinori Sato
2002 J jnl
Evaluating Influence of Compiler Optimizations on Data Speculation.
J. Inf. Sci. Eng.
Toshinori Sato, Kiichi Sugitani, Akihiko Hamano
2002 J jnl
Evaluating the impact of reissued instructions on data speculative processor performance.
Microprocess. Microsystems
Toshinori Sato
2002 — conf
Low-Cost Value Predictors Using Frequent Value Locality.
ISHPC
Toshinori Sato, Itsujiro Arita
2002 — conf
Reducing Energy Consumption via Low-Cost Value Prediction.
PATMOS
Toshinori Sato, Itsujiro Arita
2002 C conf
Simplifying Instruction Issue Logic in Superscalar Processors.
DSD
Toshinori Sato, Itsujiro Arita
2002 Misc conf
The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization.
PDPTA
Toshiyuki Yamamoto, Kou Morita, Toshinori Sato, Itsujiro Arita
2001 C conf
Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications.
PRDC
Toshinori Sato, Itsujiro Arita
2001 — conf
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse.
Euro-Par
Toshinori Sato, Itsujiro Arita
2001 B conf
In Search of Efficient Reliable Processor Design.
ICPP
Toshinori Sato, Itsujiro Arita
2001 — conf
Influence of Compiler Optimizations on Value Prediction.
HPCN Europe
Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita
2001 — conf
Tolerating Transient Faults through an Instruction Reissue Mechanism.
PDCS
Toshinori Sato, Itsujiro Arita
2000 J jnl
2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing.
IEEE J. Solid State Circuits
Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin-ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki
2000 — conf
300MHz design methodology of VU for emotion synthesis.
ASP-DAC
Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu
2000 — conf
Comprehensive Evaluation of an Instruction Reissue Mechanism.
ISPAN
Toshinori Sato, Itsujiro Arita
2000 B conf
Partial Resolution in Data Value Predictors.
ICPP
Toshinori Sato, Itsujiro Arita
2000 J jnl
Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism.
J. Syst. Archit.
Toshinori Sato
2000 A conf
Table size reduction for data value predictors by exploiting narrow width values.
ICS
Toshinori Sato, Itsujiro Arita
2000 Misc conf
The KIT COSMOS Processor: Introducing CONDOR.
PDPTA
Toshinori Sato, Itsujiro Arita
2000 J jnl
Vector Unit Architecture for Emotion Synthesis.
IEEE Micro
Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki
1999 J jnl
A Simulation Study of Combining Load Value and Address Predictors.
Int. J. High Speed Comput.
Toshinori Sato
1999 — conf
A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism.
EUROMICRO
Toshinori Sato
1999 — conf
Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure.
Euro-Par
Toshinori Sato
1999 — conf
Profile-Based Selection of Load Value and Address Predictors.
ISHPC
Toshinori Sato
1998 — conf
Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue.
EUROMICRO
Toshinori Sato
1997 — conf
Data Dependence Path Reductio with Tunneling Load Instructions.
ISHPC
Toshinori Sato