Toshinori Hosokawa

56 papers A* 1B 2C 13Misc 1Journal 9Unranked 30

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Multiple Target Seed Generation Method for Random Pattern Resistant Faults on Built-In Self-Test. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takanobu Sone, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai
2025	—	`conf`	A Don't Care Filling Method for Control Signals on State Transitions of Controllers to Minimize the Estimated Number of Test Patterns for Data-Paths. ATS Haruta Tokuta, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai
2025	—	`conf`	PBO-Based Pattern Replacement for Compacting Diagnostic Patterns to Achieve Complete Diagnostic Resolution. DFT Tatsuya Aono, Toshinori Hosokawa, Masayoshi Yoshimura, Koji Yamazaki, Masayuki Arai
2024	—	`conf`	A Low Power Oriented Multiple Target Test Generation Method for 2-Cycle Gate-Exhaustive Faults. DFT Toshinori Hosokawa, Momona Mizota, Masayoshi Yoshimura, Masayuki Arai
2024	J	`jnl`	CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayoshi Yoshimura, Atsuya Tsujikawa, Toshinori Hosokawa
2023	—	`conf`	A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage. DFT Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai
2023	—	`conf`	An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information. DFT Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi, Masayuki Arai
2023	—	`conf`	An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing. DFT Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa, Masayoshi Yoshimura
2023	—	`conf`	An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers. DFT Toshinori Hosokawa, Kyohei Iizuka, Masayoshi Yoshimura
2022	—	`conf`	CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level. DFT Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, Toshinori Hosokawa
2020	C	`conf`	A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method. IOLTS Toshinori Hosokawa, Kenichiro Misawa, Hiroshi Yamazaki, Masayoshi Yoshimura, Masayuki Arai
2020	—	`conf`	A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT. DFT Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai
2020	C	`conf`	A Test Sensitization State Compaction Method on Controller Augmentation. IOLTS Yuki Ikegaya, Toshinori Hosokawa, Yuta Ishiyama, Hiroshi Yamazaki
2020	J	`jnl`	Universal Testing for Linear Feed-Forward/Feedback Shift Registers. IEICE Trans. Inf. Syst. Hideo Fujiwara, Katsuya Fujiwara, Toshinori Hosokawa
2019	C	`conf`	A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths. IOLTS Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura
2019	C	`conf`	A Design for Testability Method for k-Cycle Capture Test Generation. IOLTS Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki
2019	—	`conf`	A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively. DFT Toshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, Masavuki Arai
2019	—	`conf`	A State Assignment Method to Improve Transition Fault Coverage for Controllers. DFT Masayoshi Yoshimura, Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa
2019	C	`conf`	A Test Generation Method Based on k-Cycle Testing for Finite State Machines. IOLTS Yuya Kinoshita, Toshinori Hosokawa, Hideo Fujiwara
2018	C	`conf`	A Capture Safe Static Test Compaction Method Based on Don't Cares. IOLTS Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura
2018	C	`conf`	A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification. IOLTS Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume
2018	C	`conf`	A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns. IOLTS Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura
2017	C	`conf`	A Diagnostic Fault Simulation Method for a Single Universal Logical Fault Model. PRDC Toshinori Hosokawa, Hideyuki Takano, Hiroshi Yamazaki, Koji Yamazaki
2017	J	`jnl`	A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa
2017	C	`conf`	A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations. PRDC Masayoshi Yoshimura, Tomohiro Bouyashiki, Toshinori Hosokawa
2017	J	`jnl`	A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation. IEICE Trans. Inf. Syst. Toshinori Hosokawa, Atsushi Hirai, Yukari Yamauchi, Masayuki Arai
2017	—	`conf`	A dynamic test compaction method on low power test generation based on capture safe test vectors. DFT Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai
2017	C	`conf`	Controller augmentation and test point insertion at RTL for concurrent operational unit testing. IOLTS Toshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, Masayoshi Yoshimura
2016	B	`conf`	A scheduling method for hierarchical testability based on test environment generation results. ETS Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
2015	—	`conf`	A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions. ATS Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa
2015	—	`conf`	A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation. ATS Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
2015	B	`conf`	A low capture power test generation method using capture safe test vectors. ETS Atsushi Hirai, Yukari Yamauchi, Toshinori Hosokawa, Masayuki Arai
2013	J	`jnl`	A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution. IEICE Trans. Inf. Syst. Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura
2013	C	`conf`	A don't care identification method for test compaction. DDECS Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura
2013	—	`conf`	A smart Trojan circuit and smart attack method in AES encryption circuits. DFTS Masayoshi Yoshimura, Amy Ogita, Toshinori Hosokawa
2010	J	`jnl`	A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. IEICE Trans. Inf. Syst. Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara
2010	C	`conf`	Evaluation of transition untestable faults using a multi-cycle capture test generation method. DDECS Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki
2008	—	`conf`	A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. ATS Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara
2007	—	`conf`	Fault-dependent/independent Test Generation Methods for State Observable FSMs. ATS Toshinori Hosokawa, Ryoichi Inoue, Hideo Fujiwara
2005	—	`conf`	An Effective Design for Hierarchical Test Generation Based on Strong Testability. Asian Test Symposium Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara
2004	J	`jnl`	A DFT Selection Method for Reducing Test Application Time of System-on-Chips. IEICE Trans. Inf. Syst. Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
2003	—	`conf`	A DFT Selection Method for Reducing Test Application Time of System-on-Chips. Asian Test Symposium Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
2003	—	`conf`	A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. Asian Test Symposium Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara
2003	—	`conf`	VCore-based design methodology. ASP-DAC Michiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida
2002	—	`conf`	A SoC Test Strategy Based on a Non-Scan DFT Method. Asian Test Symposium Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka
2002	—	`conf`	A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. Asian Test Symposium Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
2002	Misc	`conf`	A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. VTS Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
2002	—	`conf`	A Test Point Insertion Method to Reduce the Number of Test Patterns. Asian Test Symposium Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta
2002	J	`jnl`	Test sequence compaction methods for acyclic sequential circuits using a time expansion model. Syst. Comput. Jpn. Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara
2001	—	`conf`	Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. ASP-DAC Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta
1999	—	`conf`	Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. Asian Test Symposium Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara
1998	—	`conf`	An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. Asian Test Symposium Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara
1997	—	`conf`	A Partial Scan Design Method Based on n-Fold Line-up Structures. Asian Test Symposium Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu
1996	—	`conf`	A Design for testability Method Using RTL Partitioning. Asian Test Symposium Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka
1995	—	`conf`	Design for testability using register-transfer level partial scan selection. ASP-DAC Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka
1993	A*	`conf`	A State Traversal Algorithm Using a State Covariance Matrix. DAC Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin