Toshikazu Suzuki

26 papers A 1Journal 13Unranked 12

Year	Rank	Type	Title / Venue / Authors
2014	J	`jnl`	A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity. IEEE J. Solid State Circuits Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song
2013	—	`conf`	A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	J	`jnl`	A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy. IEEE J. Solid State Circuits Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi
2013	—	`conf`	Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs. ISSCC Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song
2013	J	`jnl`	Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. IEEE J. Solid State Circuits Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara
2012	—	`conf`	60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. ESSCIRC Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara
2012	—	`conf`	A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. VLSIC Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara
2012	J	`jnl`	A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Trans. Electron. Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. IEICE Electron. Express Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	A	`conf`	A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy. ISSCC Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi
2011	—	`conf`	0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. CICC Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano
2011	—	`conf`	Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme. A-SSCC Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano
2010	—	`conf`	0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. ESSCIRC Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara
2008	J	`jnl`	A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. IEEE J. Solid State Circuits Toshikazu Suzuki, Hiroyuki Yamauchi, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu
2007	J	`jnl`	A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Trans. Electron. Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami
2007	—	`conf`	A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme. CICC Toshikazu Suzuki, Hiroyuki Yamauchi, Katsuji Satomi, Hironori Akamatsu
2006	J	`jnl`	A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage ( IEICE Trans. Electron. Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami
2006	J	`jnl`	A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. IEEE J. Solid State Circuits Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi
2005	J	`jnl`	0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. IEICE Trans. Electron. Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi
2004	J	`jnl`	A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. IEEE J. Solid State Circuits Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade
2003	—	`conf`	AtelierM: a physically based interactive system for creating traditional marbling textures. GRAPHITE Xiaoyang Mao, Toshikazu Suzuki, Atsumi Imamiya
2001	—	`conf`	Simulating Marbling with Computer Graphics. VIIP Toshikazu Suzuki, Xiaoyang Mao, Atsumi Imamiya
1994	J	`jnl`	ATM adaptation layer protocol. IEEE Commun. Mag. Toshikazu Suzuki
1993	J	`jnl`	A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's. IEEE J. Solid State Circuits Hiroyuki Yamauchi, Toshikazu Suzuki, Akihiro Sawada, Tohru Iwata, Toshiaki Tsuji, Masashi Agata, Takashi Taniguchi, Yoshinori Odake, Kazuyuki Sawada, Teruhito Ohnishi, Masanori Fukumoto, Tsutomu Fujita, Michihiro Inoue