Toshikazu Sekine

34 papers C 4Journal 8Unranked 22

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Non-floating and low-power adiabatic logic circuit. IEICE Electron. Express Mei Han, Yasuhiro Takahashi, Toshikazu Sekine
2017	—	`conf`	Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture. ECCTD Yuya Kojima, Toshikazu Sekine, Yasuhiro Takahashi
2017	—	`conf`	Low power Adiabatic Logic based on 2PC2AL. ICICDT Mei Han, Yasuhiro Takahashi, Toshikazu Sekine
2017	—	`conf`	Operational amplifier based LC resonant circuit for adiabatic logic. MIXDES Yasuhiro Takahashi, Toshikazu Sekine, Mei Han
2015	—	`conf`	A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. NEWCAS Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
2015	—	`conf`	An improved estimation method of 4 port S-parameters with 2 port measurements. ECCTD Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi
2015	J	`jnl`	Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design. IET Circuits Devices Syst. Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2015	J	`jnl`	SPICE model of memristive device using Tukey window function. IEICE Electron. Express Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
2015	J	`jnl`	Two phase clocked subthreshold adiabatic logic circuit. IEICE Electron. Express Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
2014	C	`conf`	An LSI implementation of a bit-parallel cellular multiplier over GF(2 ISCAS Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2014	—	`conf`	Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation. APCCAS Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2014	—	`conf`	Power dissipation analysis of memristor for low power integrated circuit applications. APCCAS Haruki Ogata, Yasuhiro Takahashi, Toshikazu Sekine
2014	—	`conf`	Process variation verification of low-power secure CSSAL AES S-box circuit. MWSCAS Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2014	—	`conf`	Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic. APCCAS Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
2014	C	`conf`	Two phase clocking subthreshold adiabatic logic. ISCAS Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
2013	—	`conf`	An estimation method for the 3 port S-parameters with 1 port measurements. ECCTD Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi
2013	J	`jnl`	Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level. Microelectron. J. Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2013	C	`conf`	DPA resistance of charge-sharing symmetric adiabatic logic. ISCAS Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2013	—	`conf`	Low power secure CSSAL bit-parallel multiplier over GF(2 ECCTD Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2013	—	`conf`	Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks. TSP Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2012	—	`conf`	2PCDAL: Two-phase clocking dual-rail adiabatic logic. APCCAS Yasuhiro Takahashi, Zhongyu Luo, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama
2012	—	`conf`	A low-power sense amplifier for adiabatic memory using memristor. APCCAS Yuki Urata, Yasuhiro Takahashi, Toshikazu Sekine, Nazrul Anuar Nayan
2012	J	`jnl`	LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectron. J. Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine
2012	—	`conf`	Power-saving analysis of adiabatic logic in subthreshold region. ISPACS Yasuhiro Takahashi, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama
2011	—	`conf`	Low-power adiabatic SRAM. ISPACS Hides Jamima, Yasuhiro Takahashi, Toshikazu Sekine
2011	—	`conf`	Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. ISPACS Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2010	C	`conf`	4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. VLSI-SoC Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
2009	—	`conf`	4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. ECCTD Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
2009	—	`conf`	A new horizontal and vertical common subexpression elimination method for multiple constant multiplication. ICECS Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
2009	—	`conf`	Fundamental logics based on two phase clocked adiabatic static CMOS logic. ICECS Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
2009	—	`conf`	Two phase clocked adiabatic static CMOS logic. SoC Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
2007	J	`jnl`	A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
2007	J	`jnl`	VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic. IEICE Trans. Electron. Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
2006	—	`conf`	2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic. APCCAS Yasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekine, Michio Yokoyama