Toshihiro Katashita

26 papers B 1C 1Misc 1Journal 12Unranked 11
YearRankTypeTitle / Venue / Authors
2025 J jnl
Fully Quantized Matrix Arithmetic-Only BERT Model and Its FPGA-Based Accelerator.
IEEE Access
Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, Masakazu Hioki
2024 — conf
FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks.
ACNS Workshops (1)
Tatsuya Oyama, Mika Sakai, Yohei Hori, Toshihiro Katashita, Takeshi Fujino
2024 J jnl
Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation.
IEEE Access
Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, Masakazu Hioki
2021 J jnl
Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices.
IEICE Trans. Commun.
Yusuke Yano, Kengo Iokibe, Toshiaki Teshima, Yoshitaka Toyota, Toshihiro Katashita, Yohei Hori
2020 J jnl
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping.
Integr.
Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike
2019 — conf
A Deep Learning Attack Countermeasure with Intentional Noise for a PUF-Based Authentication Scheme.
SECITC
Risa Yashiro, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama
2018 J jnl
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device.
IEICE Trans. Inf. Syst.
Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike
2017 — conf
Prototype of USB stick-sized PUF module for authentication and key generation.
GCCE
Toshihiro Katashita, Yohei Hori, Yasuhiro Ogasahara
2015 J jnl
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation.
IEEE Trans. Very Large Scale Integr. Syst.
Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki
2014 J jnl
Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays.
J. Inf. Process.
Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh, Shin-ichi Kawamura, Kazukuni Kobara
2014 J jnl
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.
IEICE Trans. Electron.
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger
2013 J jnl
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata
2013 — conf
A novel smart card development platform for evaluating physical attacks and PUFs.
GCCE
Toshihiro Katashita, Akihiko Sasaki, Yohei Hori
2013 J jnl
Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption.
IEICE Trans. Inf. Syst.
Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh
2013 — conf
Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA.
GCCE
Yohei Hori, Toshihiro Katashita, Kazukuni Kobara
2012 C conf
Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI.
FDTC
Takeshi Sugawara, Daisuke Suzuki, Toshihiro Katashita
2012 J jnl
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates.
IEEE Trans. Very Large Scale Integr. Syst.
Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki
2011 — conf
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation.
HOST
Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh
2011 — conf
Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function.
ReConFig
Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh
2010 — conf
Hardware Implementations of Hash Function Luffa.
HOST
Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
2010 — conf
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs.
ReConFig
Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh
2009 — conf
Development of side-channel attack standard evaluation environment.
ECCTD
Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
2008 — conf
Enhanced Correlation Power Analysis Using Key Screening Technique.
ReConFig
Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
2007 J jnl
FPGA-Based Intrusion Detection System for 10 Gigabit Ethernet.
IEICE Trans. Inf. Syst.
Toshihiro Katashita, Yoshinori Yamaguchi, Atusi Maeda, Kenji Toda
2006 B conf
A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection.
FPL
Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi
2006 Misc conf
Highly Efficient String Matching Circuit for IDS with FPGA.
FCCM
Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi