Toshiaki Yamanaka

16 papers Journal 15Unranked 1

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	TSP integrality gap via 2-edge-connected multisubgraph problem under coincident IP optima. CoRR Toshiaki Yamanaka
2013	—	`conf`	Accuracy assessment of kinect body tracker in instant posturography for balance disorders. ISMICT Hiroyuki Funaya, Tomohiro Shibata, Yoshiro Wada, Toshiaki Yamanaka
1995	J	`jnl`	A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. IEEE J. Solid State Circuits Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome
1995	J	`jnl`	A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. IEEE J. Solid State Circuits Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida
1995	J	`jnl`	A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. IEEE J. Solid State Circuits Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome
1995	J	`jnl`	A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. IEEE J. Solid State Circuits Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida
1994	J	`jnl`	A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. IEEE J. Solid State Circuits Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki
1993	J	`jnl`	A 1.5-ns 32-b CMOS ALU in double pass-transistor logic. IEEE J. Solid State Circuits Makoto Suzuki, Norio Ohkubo, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome
1993	J	`jnl`	A 16-Mb CMOS SRAM with a 2.3- mu m IEEE J. Solid State Circuits Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nagatoshi Ohki
1992	J	`jnl`	A 1-V TFT-load SRAM using a two-step word-voltage method. IEEE J. Solid State Circuits Koichiro Ishibashi, Koichi Takasugi, Toshiaki Yamanaka, Takashi Hashimoto, Katsuro Sasaki
1992	J	`jnl`	A 1.7-V adjustable I/O interface for low-voltage fast SRAMs. IEEE J. Solid State Circuits Koichiro Ishibashi, Katsuro Sasaki, Toshiaki Yamanaka, Hiroshi Toyoshima, Fumio Kojima
1992	J	`jnl`	A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier. IEEE J. Solid State Circuits Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, Akihiro Shimizu
1990	J	`jnl`	A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current. IEEE J. Solid State Circuits Katsuro Sasaki, Koichiro Ishibashi, Katsuhiro Shimohigashi, Toshiaki Yamanaka, Nobuyuki Moriwake, Shigeru Honjo, Shuji Ikeda, Atsuyoshi Koike, Satoshi Meguro, Osamu Minato
1990	J	`jnl`	A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic. IEEE J. Solid State Circuits Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu
1990	J	`jnl`	An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell. IEEE J. Solid State Circuits Koichiro Ishibashi, Toshiaki Yamanaka, Katsuhiro Shimohigashi
1989	J	`jnl`	A 9-ns 1-Mbit CMOS SRAM. IEEE J. Solid State Circuits Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo