Toshiaki Kirihata

31 papers C 1Journal 19Unranked 11

Year	Rank	Type	Title / Venue / Authors
2018	—	`conf`	14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming. VLSI Circuits Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata
2018	J	`jnl`	80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity. IEEE J. Solid State Circuits Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer
2016	—	`conf`	80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. VLSI Circuits Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer
2016	J	`jnl`	A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. IEEE J. Solid State Circuits Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer
2016	J	`jnl`	Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias. IEEE J. Emerg. Sel. Topics Circuits Syst. Toshiaki Kirihata, John Golz, Matthew R. Wordeman, Pooja Batra, Gary W. Maier, Norman Robson, Troy L. Graves-abe, Daniel Berger, Subramanian S. Iyer
2015	—	`conf`	Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications. IRPS Chandrasekharan Kothandaraman, X. Chen, Dan Moy, Dallas Lea, Sami Rosenblatt, Faraz Khan, Derek Leu, Toshiaki Kirihata, D. Ioannou, Giuseppe La Rosa, Jeffrey B. Johnson, Norman Robson, Subramanian S. Iyer
2014	—	`conf`	Advanced memory topics. CICC Toshiaki Kirihata, Dinesh Somasekhar
2013	J	`jnl`	A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM. IEEE J. Solid State Circuits Sami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer
2013	—	`conf`	Advanced memory topics. CICC Koji Nii, Toshiaki Kirihata
2013	J	`jnl`	Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM. IEEE J. Solid State Circuits Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer
2012	—	`conf`	Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM. VLSIC Daniel Fainstein, Sami Rosenblatt, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer
2011	J	`jnl`	A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. IEEE J. Solid State Circuits John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao
2011	—	`conf`	Three Dimensional integration - Considerations for memory applications. CICC Subramanian S. Iyer, Toshiaki Kirihata, John E. Barth Jr.
2009	J	`jnl`	A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer
2008	J	`jnl`	A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2008	—	`conf`	A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS. ISSCC Gregory Uhlmann, Tony Aipperspach, Toshiaki Kirihata, K. Chandrasekharan, Yan Zun Li, Chris Paone, Brian Reed, Norman Robson, John Safran, David Schmitt, Subramanian S. Iyer
2008	—	`conf`	An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. ESSCIRC Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata
2007	—	`conf`	A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2007	—	`conf`	Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips. CICC Norman Robson, John Safran, Chandrasekharan Kothandaraman, Alberto Cestero, Xiang Chen, Raj Rajeevakumar, Alan Leslie, Dan Moy, Toshiaki Kirihata, Subramanian S. Iyer
2005	J	`jnl`	An 800-MHz embedded DRAM with a concurrent refresh mode. IEEE J. Solid State Circuits Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer
2000	J	`jnl`	A 7F IEEE J. Solid State Circuits Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman
1999	J	`jnl`	A 390-mm IEEE J. Solid State Circuits Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, Joseph M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman
1998	J	`jnl`	A 220-mm IEEE J. Solid State Circuits Toshiaki Kirihata, Martin Gall, Kohji Hosokawa, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl
1997	C	`conf`	Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
1997	J	`jnl`	Flexible test mode approach for 256-Mb DRAM. IEEE J. Solid State Circuits Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik
1996	J	`jnl`	A 286 mm IEEE J. Solid State Circuits Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii
1996	J	`jnl`	Fault-tolerant designs for 256 Mb DRAM. IEEE J. Solid State Circuits Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao
1995	J	`jnl`	A low-noise TTL-compatible CMOS off-chip driver circuit. IBM J. Res. Dev. Sang H. Dhong, Masahiro Tanaka, Steven W. Tomashot, Toshiaki Kirihata
1992	J	`jnl`	A 14-ns 14-Mb CMOS DRAM with 300-mW active power. IEEE J. Solid State Circuits Toshiaki Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa
1992	J	`jnl`	A pulsed sensing scheme with a limited bit-line swing. IEEE J. Solid State Circuits Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, T. Yoshikawa, Koji Kitamura, Sang H. Dhong
1989	J	`jnl`	A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing. IEEE J. Solid State Circuits Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano