Toru Tanzawa

46 papers C 6Journal 24Unranked 16
YearRankTypeTitle / Venue / Authors
2025 — conf
Design of Switched-Capacitor AC-DC Voltage Down-Converters for Micro-Watt Electrostatic Vibration Energy Harvesting.
NewCAS
Naoto Miyazaki, Toru Tanzawa
2025 — conf
Design of a Battery Charger Boost Converter for Extremely Low Supply Voltages Below 10 mV in Energy Harvesting: A Return-on-Investment Approach.
NewCAS
Wataru Saito, Toru Tanzawa
2025 — conf
Design of a Low-Voltage DC-DC Boost Converter Using an Enhanced Swing Colpitts Oscillator for Energy Harvesting.
NewCAS
Taisei Inaba, Tatsuta Nomura, Yohei Kotoya, Toru Tanzawa
2024 — conf
Design of Switched-Capacitor AC-DC Voltage-Down Converters Driven by Highly Resistive Energy Transducers.
DCIS
Naoto Miyazaki, Toru Tanzawa
2022 J jnl
A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers.
IEEE Access
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
2022 — conf
Antenna / On-Chip-Rectifier Co-Design Methodology for Micro-Watt Microwave Wireless Power Transfer.
MWSCAS
Takuma Hashimoto, Toru Tanzawa
2021 J jnl
A Circuit Analysis of Pre-Emphasis Pulses for RC Delay Lines.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuki Matsuyama, Toru Tanzawa
2021 J jnl
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
2020 — conf
A Design of Cold Start Charge Pump for Flexible Thermoelectric Generator with High Output Impedance.
ICECS
Kazuma Koketsu, Toru Tanzawa
2020 J jnl
Linear distribution of capacitance in Dickson charge pumps to reduce rise time.
Int. J. Circuit Theory Appl.
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
2019 — conf
A 2V 3.8µW Fully-Integrated Clocked AC-DC Charge Pump with 0.5V 500Ω Vibration Energy Harvester.
APCCAS
Hayato Kawauchi, Toru Tanzawa
2019 — conf
A Pre-Emphasis Pulse Generator Insensitive to Process Variation for Driving Large Memory and Panel Display Arrays with Minimal Delay Time.
APCCAS
Kazuki Matsuyama, Toru Tanzawa
2019 C conf
Design of Pre-Emphasis Pulses for Large Memory Arrays with Minimal Word-Line Delay Time.
ISCAS
Kazuki Matsuyama, Toru Tanzawa
2019 C conf
Toward a Minimum-Operating-Voltage Design of DC-DC Charge Pump Circuits for Energy Harvesting.
ISCAS
Shugo Tokuda, Toru Tanzawa
2018 J jnl
Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology.
IEICE Trans. Electron.
Toru Tanzawa
2018 J jnl
On the Output Impedance and an Output Current-Power Efficiency Relationship of Dickson Charge Pump Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Toru Tanzawa
2017 J jnl
An Analytical Model of Charge Pump DC-DC Voltage Multiplier Using Diodes.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Toru Tanzawa
2017 — conf
On-chip switched-capacitor DC-DC converter in memory technology: State of the art and challenges.
ECCTD
Toru Tanzawa
2016 — conf
7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.
ISSCC
Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo
2016 J jnl
An Analytical Model of AC-DC Charge Pump Voltage Multipliers.
IEICE Trans. Electron.
Toru Tanzawa
2016 — conf
Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors.
A-SSCC
Toru Tanzawa, T. Murakoshi, T. Kamijo, Tomoharu Tanaka, J. J. McNeil, K. Duesman
2015 C conf
A comprehensive optimization methodology for designing charge pump voltage multipliers.
ISCAS
Toru Tanzawa
2015 C conf
An analytical model of multi-sine AC-DC voltage multiplier.
ISCAS
Toru Tanzawa
2014 — conf
An analytical model of AC-DC voltage multipliers.
ICECS
Toru Tanzawa
2014 — conf
Design of DC-DC switched-capacitor voltage multiplier driven by DC energy transducer.
ICECS
Toru Tanzawa
2012 J jnl
A Behavior Model of an On-Chip High Voltage Generator for Fast, System-Level Simulation.
IEEE Trans. Very Large Scale Integr. Syst.
Toru Tanzawa
2010 J jnl
A Behavior Model of a Dickson Charge Pump Circuit for Designing a Multiple Charge Pump System Distributed in LSIs.
IEEE Trans. Circuits Syst. II Express Briefs
Toru Tanzawa
2010 — conf
A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories.
ESSCIRC
Toru Tanzawa, Tomoharu Tanaka, Satoru Tamada, Jiro Kishimoto, Sjigekazu Yamada, Koichi Kawai, Takaaki Ichikawa, P. Chiang, Frank Roohparvar
2010 J jnl
On Two-Phase Switched-Capacitor Multipliers With Minimum Circuit Area.
IEEE Trans. Circuits Syst. I Regul. Pap.
Toru Tanzawa
2009 — conf
A 172mm
ISSCC
Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa, Tomoharu Tanaka, Mase Taub, Darshak Udeshi, Sjigekazu Yamada, Hiroyuki Yokoyama
2009 C conf
Dickson Charge Pump Circuit Design with Parasitic Resistance in Power Lines.
ISCAS
Toru Tanzawa
2008 C conf
A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage.
ISCAS
Toru Tanzawa
2005 J jnl
A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters.
IEICE Trans. Electron.
Toru Tanzawa, Kenichi Agawa, Hiroyuki Shibayama, Ryota Terauchi, Katsumi Hisano, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Toru Takayama, Masayuki Koizumi, Fumitoshi Hatori
2004 — conf
A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter.
CICC
Toru Tanzawa, Hiroyuki Shibayama, Ryota Terauchi, Katsumi Hisano, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Toru Takayama, Kenichi Agawa, Masayuki Koizumi, Fumitoshi Hatori
2002 J jnl
A 44-mm
IEEE J. Solid State Circuits
Toru Tanzawa, Akira Umezawa, Tadayuki Taura, Hitoshi Shiga, Tokumasa Hara, Yoshinori Takano, Takeshi Miyaba, Naoya Tokiwa, Kentaro Watanabe, Hiroshi Watanabe, Kazunori Masuda, Kiyomi Naruke, Hideo Kato, Shigeru Atsumi
2002 J jnl
Circuit techniques for a 1.8-V-only NAND flash memory.
IEEE J. Solid State Circuits
Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura
2002 J jnl
High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories.
IEEE J. Solid State Circuits
Toru Tanzawa, Yoshinori Takano, Kentaro Watanabe, Shigeru Atsumi
2001 J jnl
Wordline voltage generating system for low-power low-voltage flash memories.
IEEE J. Solid State Circuits
Toru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi
2000 J jnl
A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme.
IEEE J. Solid State Circuits
Shigeru Atsumi, Akira Umezawa, Toru Tanzawa, Tadayuki Taura, Hitoshi Shiga, Yoshinori Takano, Takeshi Miyaba, Michiharu Matsui, Hiroshi Watanabe, Kazuaki Isobe, Shota Kitamura, Seiji Yamada, Masanobu Saito, Seiichi Mori, Toshiharu Watanabe
2000 J jnl
Design of a sense circuit for low-voltage flash memories.
IEEE J. Solid State Circuits
Toru Tanzawa, Yoshinori Takano, Tadayuki Taura, Shigeru Atsumi
1999 J jnl
A CMOS bandgap reference circuit with sub-1-V operation.
IEEE J. Solid State Circuits
Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi, Koji Sakui
1999 J jnl
Optimization of word-line booster circuits for low-voltage flash memories.
IEEE J. Solid State Circuits
Toru Tanzawa, Shigeru Atsumi
1998 J jnl
A multipage cell architecture for high-speed programming multilevel NAND flash memories.
IEEE J. Solid State Circuits
Ken Takeuchi, Tomoharu Tanaka, Toru Tanzawa
1997 J jnl
A compact on-chip ECC for low cost flash memories.
IEEE J. Solid State Circuits
Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi
1997 J jnl
A dynamic analysis of the Dickson charge pump circuit.
IEEE J. Solid State Circuits
Toru Tanzawa, Tomoharu Tanaka
1997 J jnl
A stable programming pulse generator for single power supply flash memories.
IEEE J. Solid State Circuits
Toru Tanzawa, Tomoharu Tanaka