Toru Shimizu

54 papers A* 2B 1C 3Misc 1Journal 20Unranked 26
YearRankTypeTitle / Venue / Authors
2024 — ed.
Proceedings of the 2nd ACM SIGSPATIAL International Workshop on Human Mobility Prediction Challenge, HuMob2024, Atlanta, GA, USA, 29 October 2024 - 1 November 2024
HuMob-Challenge@SIGSPATIAL
Takahiro Yabe, Kota Tsubouchi, Toru Shimizu
2023 J jnl
Metropolitan Scale and Longitudinal Dataset of Anonymized Human Mobility Trajectories.
CoRR
Takahiro Yabe, Kota Tsubouchi, Toru Shimizu, Yoshihide Sekimoto, Kaoru Sezaki, Esteban Moro, Alex Pentland
2022 — conf
GEO-BLEU: similarity measure for geospatial sequences.
SIGSPATIAL/GIS
Toru Shimizu, Kota Tsubouchi, Takahiro Yabe
2021 J jnl
GEO-BLEU: Similarity Measure for Geospatial Sequences.
CoRR
Toru Shimizu, Kota Tsubouchi, Takahiro Yabe
2021 — conf
Improving Land Use Classification using Human Mobility-based Hierarchical Place Embeddings.
PerCom Workshops
Toru Shimizu, Takahiro Yabe, Kota Tsubouchi
2020 — conf
Enabling Finer Grained Place Embeddings using Spatial Hierarchy from Human Mobility Trajectories.
SIGSPATIAL/GIS
Toru Shimizu, Takahiro Yabe, Kota Tsubouchi
2020 J jnl
Learning Fine Grained Place Embeddings with Spatial Hierarchy from Human Mobility Trajectories.
CoRR
Toru Shimizu, Takahiro Yabe, Kota Tsubouchi
2020 — conf
POI Atmosphere Categorization Using Web Search Session Behavior.
SIGSPATIAL/GIS
Kota Tsubouchi, Hayato Kobayashi, Toru Shimizu
2020 A* conf
Unsupervised Translation via Hierarchical Anchoring: Functional Mapping of Places across Cities.
KDD
Takahiro Yabe, Kota Tsubouchi, Toru Shimizu, Yoshihide Sekimoto, Satish V. Ukkusuri
2019 — conf
City2City: Translating Place Representations across Cities.
SIGSPATIAL/GIS
Takahiro Yabe, Kota Tsubouchi, Toru Shimizu, Yoshihide Sekimoto, Satish V. Ukkusuri
2019 J jnl
City2City: Translating Place Representations across Cities.
CoRR
Takahiro Yabe, Kota Tsubouchi, Toru Shimizu, Yoshihide Sekimoto, Satish V. Ukkusuri
2019 A* conf
Predicting Evacuation Decisions using Representations of Individuals' Pre-Disaster Web Search Behavior.
KDD
Takahiro Yabe, Kota Tsubouchi, Toru Shimizu, Yoshihide Sekimoto, Satish V. Ukkusuri
2019 J jnl
Predicting Evacuation Decisions using Representations of Individuals' Pre-Disaster Web Search Behavior.
CoRR
Takahiro Yabe, Kota Tsubouchi, Toru Shimizu, Yoshihide Sekimoto, Satish V. Ukkusuri
2019 — conf
Unsupervised Answer Retrieval with Data Fusion for Community Question Answering.
AIRS
Sosuke Kato, Toru Shimizu, Sumio Fujita, Tetsuya Sakai
2018 C conf
Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers.
ISCAS
Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2018 J jnl
Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers.
IEICE Trans. Electron.
Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2018 — conf
Pretraining Sentiment Classifiers with Unlabeled Dialog Data.
ACL (2)
Toru Shimizu, Nobuyuki Shimizu, Hayato Kobayashi
2017 J jnl
An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation.
IEICE Trans. Inf. Syst.
Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
2017 — conf
Convolutional neural network for industrial egg classification.
ISOCC
Ryota Shimizu, Shusuke Yanagawa, Toru Shimizu, Mototsugu Hamada, Tadahiro Kuroda
2017 — conf
Wireless power transfer to stacked modules for IoT sensor nodes.
ISOCC
Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2017 — conf
YJTI at the NTCIR-13 STC Japanese Subtask.
NTCIR
Toru Shimizu
2016 C conf
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis.
VLSI-SoC
Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
2016 — conf
Deep learning application trial to lung cancer diagnosis for medical sensor systems.
ISOCC
Ryota Shimizu, Shusuke Yanagawa, Yasutaka Monde, Hiroki Yamagishi, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2016 — conf
Normally-off power management for sensor nodes of global navigation satellite system.
ISOCC
Takashi Nakada, Hiroshi Nakamura, Toshifumi Nakamoto, Toru Shimizu
2014 — conf
A low power NoC router using the marching memory through type.
COOL Chips
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
2014 — conf
Data-aware power management for periodic real-time systems with non-volatile memory.
NVMSA
Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
2014 J jnl
Design Aid of Multi-core Embedded Systems with Energy Model.
Inf. Media Technol.
Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
2014 — conf
Design of a low power NoC router using Marching Memory Through type.
NOCS
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
2014 — conf
Normally-off MCU architecture for low-power sensor node.
ASP-DAC
Masanori Hayashikoshi, Yohei Sato, Hiroshi Ueki, Hiroyuki Kawai, Toru Shimizu
2014 — conf
What is a good way to expand a silicon value to a solution value?
A-SSCC
Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara
2013 J jnl
0.5 V Start-Up 87% Efficiency 0.75 mm
IEEE J. Solid State Circuits
Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu
2013 J jnl
Large-scale network organization in the avian forebrain: a connectivity matrix and theoretical analysis.
Frontiers Comput. Neurosci.
Murray Shanahan, Verner P. Bingman, Toru Shimizu, Martin Wild, Onur Güntürkün
2013 J jnl
On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes.
IEICE Trans. Electron.
Yasunobu Nakase, Yasuhiro Ido, Tsukasa Oishi, Toru Shimizu
2012 — conf
A 0.5V start-up 87% efficiency 0.75mm
CICC
Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu
2011 — conf
0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers.
A-SSCC
Yasunobu Nakase, Shinichi Hirose, Toru Goda, Kehui Hu, Hiroshi Onoda, Yasuhiro Ido, Hiroyuki Kondo, Wei Kong, Wei Zhang, Tsukasa Oishi, Shintaro Mori, Toru Shimizu
2011 J jnl
Low Power Platform for Embedded Processor LSIs.
IEICE Trans. Electron.
Toru Shimizu, Kazutami Arimoto, Osamu Nishii, Sugako Otani, Hiroyuki Kondo
2009 J jnl
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications.
IEEE J. Solid State Circuits
Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu
2008 — conf
Heterogeneous multicore SoC for secure multimedia applications.
CICC
Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu
2007 J jnl
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS.
IEICE Trans. Electron.
Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu
2007 — conf
SE4 Automotive Signal Processing Technologies.
ISSCC
Toru Shimizu, Ram Krishnamurthy
2007 J jnl
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.
IEEE J. Solid State Circuits
Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu
2006 — conf
A 40GOPS 250mW massively parallel processor based on matrix architecture.
ISSCC
Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu
2006 J jnl
Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture.
IEICE Trans. Electron.
Toru Shimizu, Masami Nakajima, Masahiro Kainaga
2006 — conf
Home-Network of a Mutual Complement Communication System by Wired and Wireless.
KES (3)
Kunihiro Yamada, Takashi Furumura, Yasuhiro Seno, Yukihisa Naoe, Kenichi Kitazawa, Toru Shimizu, Koji Yoshida, Masanori Kojima, Hiroshi Mineno, Tadanori Mizuno
2006 — conf
Spatial Relation for Geometrical / Topological Map Retrieval.
KES (2)
Toru Shimizu, Masakazu Ikezaki, Toyohide Watanabe, Taketoshi Ushiama
2005 — conf
Dual Communication System Using Wired and Wireless Correspondence in Home Network.
KES (1)
Kunihiro Yamada, Kenichi Kitazawa, Hiroki Takase, Toshihiko Tamura, Yukihisa Naoe, Takashi Furumura, Toru Shimizu, Koji Yoshida, Masanori Kojima, Tadanori Mizuno
2005 — conf
Dual Communication System Using Wired and Wireless with the Routing Consideration.
KES (1)
Kunihiro Yamada, Takashi Furumura, Yoshio Inoue, Kenichi Kitazawa, Hiroki Takase, Yukihisa Naoe, Toru Shimizu, Yoshihiko Hirata, Hiroshi Mineno, Tadanori Mizuno
2005 J jnl
Implementation of Face Recognition Processing Using an Embedded Processor.
J. Robotics Mechatronics
Hiroyuki Kondo, Masami Nakajima, Miroslaw Bober, Krzysztof Kucharski, Osamu Yamamoto, Toru Shimizu
2004 J jnl
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.
IEEE J. Solid State Circuits
Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu
2004 B conf
Dual Communication System Using Wired and Wireless Correspondence in a Small Space.
KES
Kunihiro Yamada, Yoshihiko Hirata, Yukihisa Naoe, Takashi Furumura, Yoshio Inoue, Toru Shimizu, Koji Yoshida, Masanori Kojima, Tadanori Mizuno
2002 J jnl
A new RISC processor architecture for MPEG-2 decoding.
IEEE Trans. Consumer Electron.
Kunihiro Yamada, Masanori Kojima, Toru Shimizu, Fumiaki Sato, Tadanori Mizuno
1998 Misc conf
Multimedia applications of microprocessor with embedded DRAM.
ICASSP
Yasuhiro Nunomura, Toru Shimizu, Kazunori Saitoh, Koji Tsuchihashi
1997 J jnl
M32R/D-integrating DRAM and microprocessor.
IEEE Micro
Yasuhiro Nunomura, Toru Shimizu, Osamu Tomisawa
1989 C conf
A 32-bit microprocessor with high performance bit-map manipulation instructions.
ICCD
Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito