Toru Sano

17 papers A 2B 3Journal 3Unranked 9
YearRankTypeTitle / Venue / Authors
2020 J jnl
A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications.
IEEE J. Solid State Circuits
Yutaka Yamada, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima, Ryusuke Murakami, Takashi Yoshikawa, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda
2019 — conf
A 20.5TOPS and 217.3GOPS/mm
ISSCC
Yutaka Yamada, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda, Masato Uchiyama, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Ryusuke Murakami, Takashi Yoshikawa
2015 — conf
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications.
ISSCC
Jun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori
2015 J jnl
On Estimation of Tangential Force in Railways Brake Systems by Fuzzy Inference.
J. Adv. Comput. Intell. Intell. Informatics
Toru Sano, Yasunori Endo, Shin-ichi Nakazawa, Daisuke Hijikata
2014 — conf
An evaluation of an energy efficient many-core SoC with parallelized face detection.
ASP-DAC
Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori
2014 J jnl
Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters.
IEICE Trans. Electron.
Takashi Miyamori, Hui Xu, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Jun Tanabe
2013 A conf
A near-future prediction method for low power consumption on a many-core processor.
DATE
Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto
2013 A conf
Development of low power many-core SoC for multimedia applications.
DATE
Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe
2012 — conf
A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications.
VLSIC
Hui Xu, Jun Tanabe, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Takashi Miyamori
2010 — conf
MuCCRA-3: a low power dynamically reconfigurable processor array.
ASP-DAC
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano
2010 — conf
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping.
FPT
Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
2009 — conf
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array.
ERSA
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
2009 — conf
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors.
ERSA
Toru Sano, Yoshiki Saito, Hideharu Amano
2009 B conf
Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.
FPL
Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano
2009 B conf
MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.
FPL
Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano
2008 — conf
Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors.
FPT
Takuro Nakamura, Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano
2008 B conf
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors.
FPL
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano