Toru Nakura - RankMe

96 papers A 6B 1C 8Journal 40Unranked 41

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGA. DATE Kentaroh Katoh, Toru Nakura, Haruo Kobayashi
2025	A	`conf`	High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops. ITC Kentaroh Katoh, Toru Nakura, Haruo Kobayashi
2025	J	`jnl`	Optical Pulse Detection IC LIDARX Integrated in MMX-LIDAR. IEICE Trans. Electron. Takahide Mizuno, Hirokazu Ikeda, Hiroki Senshu, Toru Nakura, Kazuhiro Umetani, Akihiro Konishi, Akihito Ogawa, Kaito Kasai, Kosuke Kawahara
2025	—	`conf`	TDR-Based S-Parameter Estimation of Signal Path to DUT Utilizing Built-In Driver and Comparator of ATE. ATS Kazuki Shirahata, Masahiro Ishida, Koji Asami, Toru Nakura, Akio Higo, Tetsuya Iizuka
2024	J	`jnl`	Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection. IEICE Electron. Express Yuta Tsuchiya, Toru Nakura
2023	—	`conf`	Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating. ISSCC Yuto Yakubo, Kazuma Furutani, Kouhei Toyotaka, Haruki Katagiri, Masashi Fujita, Munehiro Kozuma, Yoshinori Ando, Yoshiyuki Kurokawa, Toru Nakura, Shunpei Yamazaki
2023	J	`jnl`	Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinichi Nishizawa, Toru Nakura
2022	J	`jnl`	4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. IEICE Trans. Electron. Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada
2022	—	`conf`	Density Aware Cell Library Design for Design-Technology Co-Optimization. ISQED Shinichi Nishizawa, Toru Nakura
2019	J	`jnl`	A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
2019	J	`jnl`	A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. IEICE Electron. Express Wang Jing, Tetsuya Iizuka, Zule Xu, Toru Nakura
2019	J	`jnl`	Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. Daigo Takahashi, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada
2019	J	`jnl`	Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada
2018	—	`conf`	A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2018	C	`conf`	A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2018	J	`jnl`	Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2018	J	`jnl`	Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2018	J	`jnl`	Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada
2018	J	`jnl`	Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda
2018	J	`jnl`	Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	J	`jnl`	A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	J	`jnl`	A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. IEEE SENSORS Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada
2017	—	`conf`	A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	—	`conf`	CMOS-on-quartz pulse generator for low power applications. ASP-DAC Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	J	`jnl`	Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	B	`conf`	Extension of power supply impedance emulation method on ATE for multiple power domain. ETS Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	—	`conf`	Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2016	—	`conf`	A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada
2016	—	`conf`	A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
2016	J	`jnl`	An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2016	J	`jnl`	An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface. IEICE Trans. Electron. Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada
2016	—	`conf`	Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise. ISQED Masahiro Kano, Toru Nakura, Kunihiro Asada
2016	A	`conf`	Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2016	J	`jnl`	Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. J. Electron. Test. Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
2016	—	`conf`	Fully automated PLL compiler generating final GDS from specification. ISQED Toru Nakura, Kunihiro Asada
2016	—	`conf`	One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise. EWME Toru Nakura, Yuki Okamoto, Yoshio Mita, Kunihiro Asada
2016	J	`jnl`	Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. IEICE Trans. Electron. Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
2016	A	`conf`	Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2016	—	`conf`	Resonant power supply noise reduction using a triangular active charge injection. ICECS Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2015	—	`conf`	A Technique for Analyzing On-Chip Power Supply Impedance. ATS Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada
2015	—	`conf`	A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2015	C	`conf`	An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2015	J	`jnl`	Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline. IEICE Electron. Express Toru Nakura, Hiroaki Matsui, Kunihiro Asada
2015	J	`jnl`	Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer. IEICE Trans. Electron. Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Atsunori Hattori, Kunihiro Asada
2015	—	`conf`	Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2014	C	`conf`	Burst-pulse Generator based on transmission line toward sub-MMW. DDECS Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada
2014	C	`conf`	Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. DDECS Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada
2014	A	`conf`	Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. ITC Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada
2014	—	`conf`	Streaming distribution of a live seminar: Rudimentary knowledge for LSI design. EWME Toru Nakura, Kunihiro Asada
2013	—	`conf`	A Pulse Width controlled PLL and its automated design flow. ICECS Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2013	—	`conf`	An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada
2013	—	`conf`	Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator. ICECS Tomohiko Yano, Toru Nakura, Kunihiro Asada
2013	J	`jnl`	On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. IEICE Trans. Electron. Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2012	—	`conf`	7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada
2012	J	`jnl`	Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2012	—	`conf`	Impact of All-Digital PLL on SoC Testing. Asian Test Symposium Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2012	J	`jnl`	Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. IEICE Trans. Electron. Toru Nakura, Kunihiro Asada
2012	J	`jnl`	On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Trans. Electron. Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2012	A	`conf`	Power integrity control of ATE for emulating power supply fluctuations on customer environment. ITC Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
2011	J	`jnl`	1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2011	C	`conf`	Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Trans. Electron. Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy. ISOCC Teruki Nakasato, Toru Nakura, Kunihiro Asada
2010	J	`jnl`	A 8bit two stage time-to-digital converter using time difference amplifier. IEICE Electron. Express Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2010	J	`jnl`	A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2010	—	`conf`	All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. ESSCIRC Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2010	C	`conf`	Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2010	—	`conf`	Cascaded time difference amplifier using differential logic delay cell. ASP-DAC Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2010	J	`jnl`	Time Difference Amplifier with Robust Gain Using Closed-Loop Control. IEICE Trans. Electron. Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada
2010	—	`conf`	Time-to-digital converter based on time difference amplifier with non-linearity calibration. ESSCIRC Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009	—	`conf`	647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. ESSCIRC Benjamin Stefan Devlin, MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009	C	`conf`	All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009	J	`jnl`	Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. IEICE Trans. Electron. Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009	C	`conf`	Measurement of power supply noise tolerance of self-timed processor. DDECS Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda
2009	—	`conf`	Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. ACM Great Lakes Symposium on VLSI MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009	—	`conf`	SAT-based ATPG testing of inter- and intra-gate bridging faults. ECCTD Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada
2007	—	`conf`	Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. ASP-DAC Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2007	—	`conf`	Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. ISSCC Toru Nakura, Koichi Nose, Masayuki Mizuno
2007	—	`conf`	LAGS System Using Data/Instruction Grain Power Control. ISSCC Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada
2006	J	`jnl`	Autonomous IEICE Trans. Electron. Toru Nakura, Makoto Ikeda, Kunihiro Asada
2006	J	`jnl`	Feedforward Active Substrate Noise Cancelling Based on IEICE Trans. Electron. Toru Nakura, Makoto Ikeda, Kunihiro Asada
2005	—	`conf`	Autonomous di/dt noise control scheme for margin aware operation. ESSCIRC Toru Nakura, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	On-chip IEICE Trans. Electron. Toru Nakura, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs. IEICE Trans. Electron. Toru Nakura, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	Stub vs. Capacitor for Power Supply Noise Reduction. IEICE Trans. Electron. Toru Nakura, Makoto Ikeda, Kunihiro Asada
2003	—	`conf`	Theoretical study of stubs for power line noise reduction [LSI applications]. CICC Toru Nakura, Makoto Ikeda, Kunihiro Asada
2000	J	`jnl`	A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara