Toru Koizumi

19 papers A* 2A 2B 2C 5Journal 4Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
Inspex: Speculative Execution of Ready-to-Execute Loads in In-Order Cores.
IEEE Comput. Archit. Lett.
Yotaro Nada, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2025 J jnl
Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA.
IEICE Trans. Inf. Syst.
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2025 — conf
PEZY-SC4s : The Fourth Generation MIMD Many-core Processor with High Energy Efficiency and Flexibility for HPC and AI Applications.
HCS
Naoya Hatta, Shuntaro Tsunoda, Kouhei Uchida, Taichi Ishitani, Toru Koizumi, Ryota Shioya, Kei Ishii
2025 C conf
Register Bridging: A Lightweight Microarchitectural Approach for Skipping Overhead Instructions in Distance-Based ISA Processors.
ICCD
Fan Yang, Toru Koizumi, Jun Li, Shu Sugita, Yuriko Yamauchi, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie
2025 C conf
Trailing-Ones Anticipation for Reducing the Latency of the Rounding Incrementer in FP FMA Units.
ARITH
Toru Koizumi, Ryota Shioya, Takuya Yamauchi, Tomoya Adachi, Ken Namura, Jun Makino
2024 J jnl
TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA.
IEEE Comput. Archit. Lett.
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2023 J jnl
A Principal Factor of Performance in Decoupled Front-End.
IEICE Trans. Inf. Syst.
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 B conf
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA.
CC
Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2023 C conf
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS.
ISCAS
Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2023 A* conf
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors.
MICRO
Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 A conf
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA.
DATE
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2022 A conf
T-SKID: Predicting When to Prefetch Separately from Address Prediction.
DATE
Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2021 C conf
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end.
ICCD
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2021 C conf
Compiling and Optimizing Real-world Programs for STRAIGHT ISA.
ICCD
Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2020 B conf
A High-Performance Out-of-Order Soft Processor Without Register Renaming.
FPL
Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2019 — conf
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor.
FPT
Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima
2018 — conf
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming.
FPT
Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2018 — conf
Reduction of Instruction Increase Overhead by STRAIGHT Compiler.
CANDAR Workshops
Toru Koizumi, Satoshi Nakae, Akifumi Fukuda, Hidetsugu Irie, Shuichi Sakai
2018 A* conf
STRAIGHT: Hazardless Processor Architecture Without Register Renaming.
MICRO
Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai