| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2026 | J | jnl |
IEEE J. Solid State Circuits
|
| 2025 | J | jnl |
IEEE Micro
|
| 2025 | J | jnl |
IEEE Micro
|
| 2024 | — | conf |
NewCAS
|
| 2023 | J | jnl |
IEEE J. Solid State Circuits
|
| 2023 | C | conf |
ISCAS
|
| 2023 | C | conf |
ISCAS
|
| 2022 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2022 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2022 | C | conf |
ISCAS
|
| 2022 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2022 | J | jnl |
IEEE Open J. Circuits Syst.
|
| 2021 | — | conf |
ISSCC
|
| 2020 | J | jnl |
IEEE J. Solid State Circuits
|
| 2019 | C | conf |
ISCAS
|
| 2018 | C | conf |
ISCAS
|
| 2017 | C | conf |
ISCAS
|
| 2013 | — | conf |
ISSCC
|
| 2012 | — | conf |
ISSCC
|
| 2004 | — | conf |
Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization.
ISCAS (3)
|