Tong Lin

30 papers B 1C 14Journal 11Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
Integrated Circuit Image Synthesis for Unsupervised Circuit Annotation via Shape Consistent Image Translation.
IEEE Intell. Syst.
Yee-Yang Tee, Xuenong Hong, Deruo Cheng, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee
2025 J jnl
GNNReveal: A Novel Graph-Neural-Network-Based Attack Method for Integrated Circuit Logic Gate Decamouflaging.
IEEE Intell. Syst.
Xuenong Hong, Yee-Yang Tee, Zilong Hu, Tong Lin, Yiqiong Shi, Deruo Cheng, Bah-Hwee Gwee
2025 C conf
Long-Short-GNN: A Novel Graph Neural Network for Detecting FPGA IP Circuits for Hardware Assurance.
ISCAS
Heyi Zhang, Tong Lin, Feng Ji, Deruo Cheng, Yiqiong Shi, Bah-Hwee Gwee
2025 C conf
Multiple Hypothesis Testing for SEM Image Processing: A Case Study on Standard Cell Partition.
ISCAS
Xiaoyu Ma, Yizhen Li, Feng Ji, Tong Lin, Yiqiong Shi, Deruo Cheng, Bah-Hwee Gwee
2025 C conf
SSRNet: Few-shot IC Segmentation in Automated PCB Image Processing.
ISCAS
Yuhang Wang, Xinrui Wang, Deruo Cheng, Tong Lin, Feng Ji, Yiqiong Shi, Bah-Hwee Gwee
2024 J jnl
Integrated Circuit Mask-Generative Adversarial Network for Circuit Annotation With Targeted Data Augmentation.
IEEE Intell. Syst.
Yee-Yang Tee, Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee
2024 C conf
MLConnect: A Machine Learning Based Connection Prediction Framework for Error Correction in Recovered Circuit.
ISCAS
Xuenong Hong, Zilong Hu, Han Zhang, Yee-Yang Tee, Tong Lin, Yiqiong Shi, Deruo Cheng, Bah-Hwee Gwee
2023 C conf
GRACER: Graph-Based Standard Cell Recognition in IC Images for Hardware Assurance.
IECON
Erdong Huang, Xuenong Hong, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee
2023 J jnl
GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning.
IEEE Trans. Artif. Intell.
Xuenong Hong, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee
2023 J jnl
Patch-Based Adversarial Training for Error-Aware Circuit Annotation of Delayered IC Images.
IEEE Trans. Circuits Syst. II Express Briefs
Yee-Yang Tee, Xuenong Hong, Deruo Cheng, Chye-Soon Chee, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee
2023 C conf
SEM2GDS: A Deep-Learning Based Framework To Detect Malicious Modifications In IC Layout.
ISCAS
Tong Lin, Yiqiong Shi, Bah-Hwee Gwee
2022 J jnl
Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision.
IET Circuits Devices Syst.
Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh
2022 J jnl
Unsupervised Domain Adaptation with Histogram-gated Image Translation for Delayered IC Image Analysis.
CoRR
Yee-Yang Tee, Deruo Cheng, Chye-Soon Chee, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee
2021 B conf
Joint Anomaly Detection and Inpainting for Microscopy Images Via Deep Self-Supervised Learning.
ICIP
Ling Huang, Deruo Cheng, XuLei Yang, Tong Lin, Yiqiong Shi, Kaiyi Yang, Bah-Hwee Gwee, Bihan Wen
2019 J jnl
A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images.
IEEE Intell. Syst.
Deruo Cheng, Yiqiong Shi, Bah-Hwee Gwee, Kar-Ann Toh, Tong Lin
2019 C conf
Global Template Projection and Matching Method for Training-Free Analysis of Delayered IC Images.
ISCAS
Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh
2018 — conf
Deep Learning for Automatic IC Image Analysis.
DSP
Xuenong Hong, Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee
2018 J jnl
Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images.
IEEE Trans. Circuits Syst. II Express Briefs
Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh
2018 — conf
Single-Event-Transient Resilient Memory for DSP in Space Applications.
DSP
Ne Kyaw Zwa Lwin, H. Sivaramakrishnan, Kwen-Siong Chong, Tong Lin, Wei Shu, Joseph S. Chang
2017 J jnl
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template.
IEEE Trans. Very Large Scale Integr. Syst.
Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2016 C conf
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process.
ISCAS
Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang
2016 C conf
Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process.
ISCAS
Jize Jiang, Wei Shu, Kwen-Siong Chong, Tong Lin, Ne Kyaw Zwa Lwin, Joseph Sylvester Chang, Jingyuan Liu
2015 C conf
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline.
ISCAS
Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2014 — conf
Fully-Additive printed electronics on flexible substrates: A Fully-Additive RFID tag.
MWSCAS
Tong Ge, Joseph S. Chang, Tong Lin, Lei Zhang, Lim Geok Soon
2014 — conf
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process.
MWSCAS
Joseph S. Chang, Kwen-Siong Chong, Wei Shu, Tong Lin, Jize Jiang, Ne Kyaw Zwa Lwin, Yang Kang
2013 C conf
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic.
ISCAS
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2013 J jnl
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive V
IEEE J. Solid State Circuits
Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2012 C conf
A comparative study on asynchronous Quasi-Delay-Insensitive templates.
ISCAS
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2012 C conf
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2009 C conf
Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic.
ISCAS
Tong Lin, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang