Tomoyuki Nakabayashi

11 papers Misc 1Journal 3Unranked 7
YearRankTypeTitle / Venue / Authors
2014 — conf
Co-simulation framework for streamlining microprocessor development on standard ASIC design flow.
ASP-DAC
Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo
2014 — conf
Detail Design and Evaluation of Fab Cache.
CANDAR
Takaki Okamoto, Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo
2013 J jnl
Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor.
IET Comput. Digit. Tech.
Takahiro Sasaki, Tomoyuki Nakabayashi, Kazumasa Nomura, Kazuhiko Ohno, Toshio Kondo
2013 — conf
Dynamic BTB Resizing for Variable Stages Superscalar Architecture.
CANDAR
Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo
2013 J jnl
Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip.
Int. J. Netw. Comput.
Tomoyuki Nakabayashi, Takahiro Sasaki, Hitoshi Nakamura, Kazuhiko Ohno, Toshio Kondo
2013 — conf
FabCache: Cache Design Automation for Heterogeneous Multi-core Processors.
CANDAR
Takaki Okamoto, Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo
2012 J jnl
Design and evaluation of variable stages pipeline processor with low-energy techniques.
IET Comput. Digit. Tech.
Tomoyuki Nakabayashi, Takahiro Sasaki, I. K. Ohno, Toshio Kondo
2012 Misc conf
Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture.
ICNC
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
2011 — conf
Design and evaluation of variable stages pipeline processor chip.
ASP-DAC
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
2011 — conf
Low power semi-static TSPC D-FFs using split-output latch.
ISOCC
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
2010 — conf
Design and Evaluation of Variable Stages Pipeline Processor Chip.
ISIA
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo