Tomonori Sekiguchi

22 papers A 1Journal 15Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 20-GHz Low-Noise RF Pulse Generator for Silicon Quantum Computer with 137.4-fs Jitter.
IEICE Trans. Electron.
Takayasu Norimatsu, Yusuke Wachi, Takuji Miki, Yusuke Kanno, Ryozo Takahashi, Takashi Ogawa, Takeru Utsugi, Tomonori Sekiguchi, Makoto Nagata, Hiroyuki Mizuno
2024 J jnl
Generating Shuttling Procedures for Constrained Silicon Quantum Dot Array.
CoRR
Naoto Sato, Tomonori Sekiguchi, Takeru Utsugi, Hiroyuki Mizuno
2020 J jnl
A 22-ng/ $\surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction Techniques.
IEEE J. Solid State Circuits
Yuki Furubayashi, Takashi Oshima, Taizo Yamawaki, Keiki Watanabe, Keijiro Mori, Naoki Mori, Akira Matsumoto, Yudai Kamada, Atsushi Isobe, Tomonori Sekiguchi
2019 — conf
A 22ng/√Hz 17mW MEMS Accelerometer with Digital Noise-Reduction Techniques.
ISSCC
Yuki Furubayashi, Takashi Oshima, Taizo Yamawaki, Keiki Watanabe, Keijiro Mori, Naoki Mori, Akira Matsumoto, Hideto Kazama, Yudai Kamada, Atsushi Isobe, Tomonori Sekiguchi
2018 — conf
Design of Perforated Membrane for Low-Noise Capacitive MEMS Accelerometers.
IEEE SENSORS
Atsushi Isobe, Yudai Kamada, Takashi Oshima, Yuki Furubayashi, Noriyuki Sakuma, Chisaki Takubo, Yasushi Tainaka, Keiki Watanabe, Tomonori Sekiguchi
2016 — conf
A concentrated springs architecture for single-digit frequency symmetry in Si MEMS gyroscope.
IEEE SENSORS
Joan Giner, Yuhua Zhang, Takashi Shiota, Daisuke Maeda, Kazuo Ono, Shinya Kajiyama, Takashi Oshima, Taizo Yamawaki, Tomonori Sekiguchi
2016 — conf
A low 1/f-noise accelerometer frontend using chopper stabilization at a frequency matched with a notch of quantization noise.
IEEE SENSORS
Kazuo Ono, Daisuke Maeda, Takashi Oshima, Toshiaki Nakamura, Joan Giner, Tomonori Sekiguchi
2012 J jnl
A Low-
IEICE Trans. Electron.
Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh
2012 J jnl
Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays.
IEICE Trans. Electron.
Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh
2011 J jnl
1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing.
IEEE J. Solid State Circuits
Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa
2010 J jnl
0.5-V Low- V
IEEE J. Solid State Circuits
Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi
2009 — conf
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays.
ISSCC
Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh
2008 J jnl
Memory at VLSI Circuits Symposium.
IEEE J. Solid State Circuits
Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi
2007 J jnl
Long-Retention-Time, High-Speed DRAM Array with 12-
IEICE Trans. Electron.
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara
2006 A conf
A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-V
ISLPED
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi
2006 J jnl
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM.
IEEE J. Solid State Circuits
Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara
2005 — conf
A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup.
ICC
Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara
2002 J jnl
A low-impedance open-bitline array for multigigabit DRAM.
IEEE J. Solid State Circuits
Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura
2001 J jnl
A multigigabit DRAM technology with 6F
IEEE J. Solid State Circuits
Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh
1997 J jnl
The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory.
IEEE J. Solid State Circuits
Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya
1995 J jnl
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.
IEEE J. Solid State Circuits
Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda
1995 J jnl
Low-noise, high-speed data transmission using a ringing-canceling output buffer.
IEEE J. Solid State Circuits
Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki