Tomokazu Yoneda

57 papers A* 1A 8B 8C 3Misc 4Journal 19Unranked 14

Year	Rank	Type	Title / Venue / Authors
2017	J	`jnl`	An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan. IEICE Trans. Inf. Syst. Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue
2017	J	`jnl`	An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. Integr. Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue
2017	B	`conf`	Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions. ETS Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue, Alex Orailoglu
2017	—	`conf`	Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. ATS Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu
2016	B	`conf`	Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. ETS Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue
2016	J	`jnl`	Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair. IEICE Trans. Inf. Syst. Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue
2015	B	`conf`	An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. ETS Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato
2014	A	`conf`	Memory block based scan-BIST architecture for application-dependent FPGA testing. FPGA Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue
2014	—	`conf`	Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units. ATS Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue
2012	J	`jnl`	A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
2012	A	`conf`	A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. ITC Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue
2012	A	`conf`	DART: Dependable VLSI test architecture and its implementation. ITC Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
2012	J	`jnl`	Test Pattern Ordering and Selection for High Quality Test Set under Constraints. IEICE Trans. Inf. Syst. Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hideo Fujiwara
2011	J	`jnl`	Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J. Electron. Test. Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
2011	J	`jnl`	Delay Testing: Improving Test Quality and Avoiding Over-testing. Inf. Media Technol. Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
2011	J	`jnl`	Delay Testing: Improving Test Quality and Avoiding Over-testing. IPSJ Trans. Syst. LSI Des. Methodol. Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
2011	A	`conf`	Faster-than-at-speed test for increased test quality and in-field reliability. ITC Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara
2011	B	`conf`	Temperature-Variation-Aware Test Pattern Optimization. ETS Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
2010	C	`conf`	Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
2010	J	`jnl`	Design and Optimization of Transparency-Based TAM for SoC Test. IEICE Trans. Inf. Syst. Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
2010	—	`conf`	RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC. APCCAS Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda, Hideo Fujiwara
2010	—	`conf`	Seed Ordering and Selection for High Quality Delay Test. Asian Test Symposium Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara
2010	B	`conf`	Test pattern selection to optimize delay test quality with a limited size of test set. ETS Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara
2010	Misc	`conf`	Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
2009	B	`conf`	Partial Scan Approach for Secret Information Protection. ETS Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
2009	—	`conf`	Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. ASP-DAC Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
2008	J	`jnl`	A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
2008	J	`jnl`	Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. IEICE Trans. Inf. Syst. Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
2008	—	`conf`	Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. ATS Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
2008	J	`jnl`	NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints. IEICE Trans. Inf. Syst. Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
2008	J	`jnl`	On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time. IEICE Trans. Inf. Syst. Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
2008	J	`jnl`	Scheduling Power-Constrained Tests through the SoC Functional Bus. IEICE Trans. Inf. Syst. Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
2008	J	`jnl`	Test Scheduling for Multi-Clock Domain SoCs under Power Constraint. IEICE Trans. Inf. Syst. Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
2008	J	`jnl`	Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. IEICE Trans. Inf. Syst. Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
2008	A	`conf`	Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. DATE Tomokazu Yoneda, Hideo Fujiwara
2007	A*	`conf`	A DFT Method for Time Expansion Model at Register Transfer Level. DAC Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara
2007	—	`conf`	Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing. ATS Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
2007	—	`conf`	Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. ASP-DAC Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
2007	A	`conf`	Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. DATE Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara
2007	B	`conf`	Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. ETS Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
2007	C	`conf`	Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. ISCAS Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara
2007	Misc	`conf`	TAM Design and Optimization for Transparency-Based SoC Test. VTS Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
2007	—	`conf`	Test Scheduling for Memory Cores with Built-In Self-Repair. ATS Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara
2007	—	`conf`	Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip. ATS Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
2007	Misc	`conf`	Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. VTS Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
2006	J	`jnl`	A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. IEICE Trans. Inf. Syst. Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
2006	—	`conf`	A memory grouping method for sharing memory BIST logic. ASP-DAC Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
2006	J	`jnl`	Design for consecutive transparency method of RTL circuits. Syst. Comput. Jpn. Tomokazu Yoneda, Hideo Fujiwara
2006	C	`conf`	Power-Constrained SOC Test Schedules through Utilization of Functional Buses. ICCD Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
2006	A	`conf`	Power-constrained test scheduling for multi-clock domain SoCs. DATE Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
2005	—	`conf`	A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
2005	—	`conf`	Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. Asian Test Symposium Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara
2004	B	`conf`	An efficient scan tree design for test time reduction. ETS Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard
2003	A	`conf`	Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. ITC Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara
2003	Misc	`conf`	Design for Consecutive Transparency of Cores in System-on-a-Chip. VTS Tomokazu Yoneda, Hideo Fujiwara
2002	J	`jnl`	Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. J. Electron. Test. Tomokazu Yoneda, Hideo Fujiwara
2001	—	`conf`	A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. Asian Test Symposium Tomokazu Yoneda, Hideo Fujiwara