Tomohiro Yoneda

89 papers A* 3A 2B 5C 13Journal 30Unranked 36

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	An FPGA-based rapid-prototyping platform for spintronics-based edge-computing hardware. ISMVL Daisuke Suzuki, Akira Tamakoshi, Tomohiro Yoneda, Masanori Natsui, Yasuhiro Takako, Takahiro Hanyu
2025	—	`conf`	Implementation of an MRAM-Based Edge AI Hardware with a Fine-Grained Power-Gating Technique. ISMVL Tomohiro Yoneda, Yasuhiro Takako, Akira Tamakoshi, Masanori Natsui, Daisuke Suzuki, Takahiro Hanyu
2023	—	`conf`	A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs. MCSoC Yuji Yamada, Nesrine Berjab, Tomohiro Yoneda, Kenji Kise
2020	—	`conf`	Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices. ASYNC Tomohiro Yoneda, Masashi Imai
2019	J	`jnl`	Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133). NII Shonan Meet. Rep. Tomohiro Yoneda, Peter A. Beerel, Alex Yakovlev, Masashi Imai
2019	—	`conf`	Hardware Trojan Insertion and Detection in Asynchronous Circuits. ASYNC Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
2018	J	`jnl`	MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
2018	—	`conf`	Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. ASYNC Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda
2017	—	`conf`	MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda
2017	—	`conf`	Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip. ICICDT Hai-Phong Phan, Xuan-Tu Tran, Tomohiro Yoneda
2017	J	`jnl`	Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
2016	—	`conf`	A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks. MCSoC Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
2016	C	`conf`	A task allocation method for the DTTR scheme based on task scheduling of fault patterns. ISCAS Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
2016	J	`jnl`	An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis. Sci. Comput. Program. Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers
2016	—	`conf`	Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance. MCSoC Sarat Yoowattana, Tomohiro Yoneda
2016	—	`conf`	The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. NOCS Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda
2015	C	`conf`	A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. ICCD Tomohiro Yoneda, Masashi Imai
2015	—	`conf`	Dependable real-time task execution scheme for a many-core platform. DFTS Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise
2015	J	`jnl`	Novel Implementation Method of Multiple-Way Asynchronous Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masashi Imai, Tomohiro Yoneda
2014	—	`conf`	An NoC-based evaluation platform for safety-critical automotive applications. APCCAS Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura
2014	—	`conf`	Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits. APCCAS Masashi Imai, Tomohiro Yoneda
2014	C	`conf`	Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. FMICS Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers
2014	J	`jnl`	High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
2014	C	`conf`	Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. ISCAS Masashi Imai, Tomohiro Yoneda
2013	J	`jnl`	Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories. IEICE Trans. Inf. Syst. Masashi Imai, Tomohiro Yoneda
2013	J	`jnl`	Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). NII Shonan Meet. Rep. Tomohiro Yoneda, José Flich Cardo, Jiang Xu, Michihiro Koibuchi
2012	—	`conf`	An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip. MCSoC Hiroshi Saito, Tomohiro Yoneda, Yuichi Nakamura
2012	—	`conf`	Dependable routing in multi-chip NoC platforms for automotive applications. DFT Tomohiro Yoneda, Masashi Imai
2012	C	`conf`	Multi-chip NoCs for Automotive Applications. PRDC Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2012	C	`conf`	Performance Modeling and Analysis of On-chip Networks for Real-Time Applications. PRDC Masashi Imai, Tomohiro Yoneda
2011	C	`ed.`	17th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2011, Pasadena, CA, USA, December 12-14, 2011 PRDC Leon Alkalai, Timothy Tsai, Tomohiro Yoneda
2011	—	`conf`	A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano
2011	—	`conf`	Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories. DFT Masashi Imai, Tomohiro Yoneda
2011	—	`conf`	Improving Dependability and Performance of Fully Asynchronous On-chip Networks. ASYNC Masashi Imai, Tomohiro Yoneda
2011	J	`jnl`	Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Scott Little, David Walter, Chris J. Myers, Robert A. Thacker, Satish Batchu, Tomohiro Yoneda
2010	C	`conf`	A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. ISCAS Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Takashi Nanya
2010	J	`jnl`	Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol. IEICE Trans. Inf. Syst. Chammika Mannakkara, Tomohiro Yoneda
2010	J	`jnl`	Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement. IEEE Trans. Computers Hao Zheng, Haiqiong Yao, Tomohiro Yoneda
2010	J	`jnl`	Preface. Int. J. Found. Comput. Sci. Kedar S. Namjoshi, Tomohiro Yoneda
2009	J	`jnl`	A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. Inf. Media Technol. Naohiro Hamada, Yuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
2009	J	`jnl`	A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. IPSJ Trans. Syst. LSI Des. Methodol. Naohiro Hamada, Yuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
2009	C	`conf`	N-way ring and square arbiters. ICCD Masashi Imai, Tomohiro Yoneda, Takashi Nanya
2009	—	`conf`	Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs. ISVLSI Hao Zheng, Haiqiong Yao, Tomohiro Yoneda
2008	J	`jnl`	A Conservative Framework for Safety-Failure Checking. IEICE Trans. Inf. Syst. Frédéric Béal, Tomohiro Yoneda, Chris J. Myers
2008	—	`conf`	A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD Naohiro Hamada, Yuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
2008	—	`conf`	Asynchronous pipeline controller based on early acknowledgement protocol. ACSD Chammika Mannakkara, Tomohiro Yoneda
2008	J	`jnl`	Hazard Checking of Timed Asynchronous Circuits Revisited. Fundam. Informaticae Frédéric Béal, Tomohiro Yoneda, Chris J. Myers
2008	J	`jnl`	Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David Walter, Scott Little, Chris J. Myers, Nicholas Seegmiller, Tomohiro Yoneda
2007	B	`ed.`	Automated Technology for Verification and Analysis, 5th International Symposium, ATVA 2007, Tokyo, Japan, October 22-25, 2007, Proceedings ATVA Kedar S. Namjoshi, Tomohiro Yoneda, Teruo Higashino, Yoshio Okamura
2007	J	`jnl`	Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
2007	—	`conf`	Hazard Checking of Timed Asynchronous Circuits Revisited. ACSD Frédéric Béal, Tomohiro Yoneda, Chris J. Myers
2007	J	`jnl`	Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
2007	—	`conf`	Symbolic Model Checking of Analog/Mixed-Signal Circuits. ASP-DAC David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda
2007	J	`jnl`	Synthesis of Timed Circuits Based on Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tomohiro Yoneda, Chris J. Myers
2006	B	`conf`	Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. ATVA Tomohiro Yoneda, Chris J. Myers
2006	C	`conf`	ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. CIT Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
2006	A	`conf`	Verification of analog/mixed-signal circuits using labeled hybrid petri nets. ICCAD Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda
2006	J	`jnl`	Verification of timed circuits with failure-directed abstractions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
2005	J	`jnl`	Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation. IEICE Trans. Inf. Syst. Tomoya Kitai, Tomohiro Yoneda, Chris J. Myers
2005	—	`conf`	High Level Synthesis of Timed Asynchronous Circuits. ASYNC Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers
2005	J	`jnl`	Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. IEICE Trans. Inf. Syst. Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers
2004	B	`conf`	Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. ATVA Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers
2004	—	`conf`	Synthesis of Speed Independent Circuits Based on Decomposition. ASYNC Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers
2004	B	`conf`	Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. ATVA Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda
2003	A	`conf`	Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. ICCAD Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
2003	C	`conf`	Verification of Timed Circuits with Failure Directed Abstractions. ICCD Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
2002	A*	`conf`	Automatic Derivation of Timing Constraints by Failure Analysis. CAV Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers
2002	C	`conf`	Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers
2002	J	`jnl`	Modular Synthesis of Timed Circuits Using Partial Order Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tomohiro Yoneda, Eric Mercer, Chris Myers
2002	—	`conf`	Modular Synthesis of Timed Circuits using Partial Order Reduction. Theory and Practice of Timed Systems @ ETAPS Eric Mercer, Chris J. Myers, Tomohiro Yoneda
2001	—	`conf`	Conformance and mirroring for timed asychronous circuits. ASP-DAC Bin Zhou, Tomohiro Yoneda, Bernd-Holger Schlingloff
2001	J	`jnl`	Efficient verification by exploiting symmetry and abstraction. Syst. Comput. Jpn. Hiroshi Toshima, Tomohiro Yoneda
2001	—	`conf`	Framework of Timed Trace Theoretic Verification Revisited. Asian Test Symposium Bin Zhou, Tomohiro Yoneda, Chris J. Myers
2001	C	`conf`	Partial Order Reduction in Verification of Wheel Structured Parameterized Circuits. PRDC Tomoya Kitai, Tomohiro Yoneda
2001	J	`jnl`	Verification of asynchronous circuits based on zero-suppressed BDDs. Syst. Comput. Jpn. Koichi Masukura, Minoru Tomisaka, Tomohiro Yoneda
2000	A*	`conf`	VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits. CAV Tomohiro Yoneda
1999	—	`conf`	A Self-Timed Implementation of Boolean Functions. ASYNC Märt Saarepera, Tomohiro Yoneda
1999	—	`conf`	Timed Trace Theoretic Verification Using Partial Order Reduction. ASYNC Tomohiro Yoneda, Hiroshi Ryu
1999	—	`conf`	Verification of Abstracted Instruction Cache of TITAC2: A Case Study. VLSI Tomohiro Yoneda
1998	—	`conf`	Verification of Bounded Delay Asynchronous Circuits with Timed Traces. AMAST Tomohiro Yoneda, Bin Zhou, Bernd-Holger Schlingloff
1998	—	`conf`	Verification of Parameterized Asynchronous Circuits: A Case Study. ACSD Tomohiro Yoneda, Yutaka Ohtsuka, Märt Saarepera
1997	J	`jnl`	Efficient Verification of Parallel Real-Time Systems. Formal Methods Syst. Des. Tomohiro Yoneda, Bernd-Holger Schlingloff
1997	J	`jnl`	Verification of asynchronous logic circuit design using process algebra. Syst. Comput. Jpn. Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya
1996	B	`conf`	BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets. FMCAD Tomohiro Yoneda, Hideyuki Hatori, Atsushi Takahara, Shin-ichi Minato
1996	—	`conf`	Using partial orders for trace theoretic verification of asynchronous circuits. ASYNC Tomohiro Yoneda, Takashi Yoshikawa
1993	A*	`conf`	Efficient Verification of Parallel Real-Time Systems. CAV Tomohiro Yoneda, Atsufumi Shibayama, Bernd-Holger Schlingloff, Edmund M. Clarke
1991	J	`jnl`	Acceleration of timing verification method based on time petri nets. Syst. Comput. Jpn. Tomohiro Yoneda, Yoshihiro Tohma, Yutaka Kondo
1989	—	`conf`	A fast timing verification method based on the independence of units. FTCS Tomohiro Yoneda, Kazutoshi Nakade, Yoshihiro Tohma
1985	J	`jnl`	Interrupt handling in the loosely synchronized TMR system. Syst. Comput. Jpn. Tomohiro Yoneda, Takashi Suzuoka, Yoshihiro Tohma