Tomoaki Yabe - RankMe

17 papers A 2Journal 7Unranked 8

Year	Rank	Type	Title / Venue / Authors
2014	J	`jnl`	A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. IEEE J. Solid State Circuits Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa
2013	—	`conf`	A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. ISSCC Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa
2012	—	`conf`	A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs. VLSIC Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe
2012	—	`conf`	Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction. ICICDT Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe
2011	J	`jnl`	A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. IEEE J. Solid State Circuits Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe
2011	—	`conf`	A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. A-SSCC Keiichi Kushida, Osamu Hirabayashi, Fumihiko Tachibana, Hiroyuki Hara, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Yuki Fujimura, Yusuke Niki, Miyako Shizuno, Shinichi Sasaki, Tomoaki Yabe
2010	J	`jnl`	A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers. IEEE J. Solid State Circuits Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Yuki Fujimura, Tomoaki Yabe
2010	—	`conf`	A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm ISSCC Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe
2009	J	`jnl`	A 0.7 V Single-Supply SRAM With 0.495 µm IEEE J. Solid State Circuits Keiichi Kushida, Azuma Suzuki, Gou Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, Takahiko Sasaki, Akira Katayama, Yuki Fujimura, Tomoaki Yabe
2009	—	`conf`	A process-variation-tolerant dual-power-supply SRAM with 0.179µm ISSCC Osamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe
2008	—	`conf`	A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell. ISSCC Atsushi Kawasumi, Tomoaki Yabe, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Akihito Tohata, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Nobuaki Otsuka
2008	A	`conf`	Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation. ITC Akira Katayama, Tomoaki Yabe, Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Nobuaki Otsuka
2002	A	`conf`	DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. ITC Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka
1998	—	`conf`	A DRAM module generator with an expandable cell array scheme. CICC Hideki Takeuchi, Tomoaki Yabe, Shinji Miyano, Takehiko Hojo, Motohiro Enkaku, Masaaki Yamada, Masami Murakata
1998	J	`jnl`	A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator. IEEE J. Solid State Circuits Tomoaki Yabe, Shinji Miyano, Katsuhiko Sato, Masaharu Wada, Ryo Haga, Osamu Wada, Motohiro Enkaku, Takehiko Hojyo, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Kenji Numata
1995	J	`jnl`	A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM. IEEE J. Solid State Circuits Shinji Miyano, Kenji Numata, Katsuhiko Sato, Tomoaki Yabe, Masaharu Wada, Ryo Haga, Motohiro Enkaku, Masazumi Shiochi, Yutaka Kawashima, Masayuki Iwase, Masahisa Ohgata, Junpei Kumagai, Takeshi Yoshida, Masaomi Sakurai, Seiji Kaki, Narutoshi Yanagiya, Hiroshi Shinya, Tohm Fumyama, Paul Hansen, Marc Hannah, Michael Nagy, Anan Nagarajan, Mana Rungsea
1990	J	`jnl`	A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell. IEEE J. Solid State Circuits Takayuki Ootani, Shigeyuki Hayakawa, Masakazu Kakumu, Akira Aona, Masaaki Kinugawa, Hideki Takeuchi, Kazuhiro Noguchi, Tomoaki Yabe, Katsuhiko Sato, Kenji Maeguchi, Kiyofumi Ochii