Tomasz S. Czajkowski

25 papers A* 2A 7B 3C 1Misc 5Journal 5Unranked 2

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Protean Compiler: An Agile Framework to Drive Fine-grain Phase Ordering. CoRR Amir H. Ashouri, Shayan Shirahmad Gale Bagi, Kavin Satheeskumar, Tejas Srikanth, Jonathan Zhao, Ibrahim Saidoun, Ziwen Wang, Bryan Chan, Tomasz S. Czajkowski
2025	—	`conf`	Stream-Aware Intelligent Memory Controller through HW/SW Co-Design. MEMSYS Abdelrhman Mohamed Abotaleb, Maziar Goudarzi, Tomasz S. Czajkowski, Reza Azimi, Mohamed Hassan
2024	B	`conf`	RoDMap: A Reserve-on-Demand Mapper for Spatially-Configured Coarse-Grained Reconfigurable Arrays. ICPP Kyle Zhao Bin Chen, Tarek S. Abdelrahman, Reza Azimi, Tomasz S. Czajkowski, Maziar Goudarzi
2024	Misc	`conf`	Work-in-Progress:ACPO: An AI-Enabled Compiler Framework. CASES Amir H. Ashouri, Muhammad Asif Manzoor, Minh Vu, Raymond Zhang, Ziwen Wang, Angel Zhang, Bryan Chan, Tomasz S. Czajkowski, Yaoqing Gao
2023	J	`jnl`	ACPO: AI-Enabled Compiler-Driven Program Optimization. CoRR Amir H. Ashouri, Muhammad Asif Manzoor, Duc Minh Vu, Raymond Zhang, Ziwen Wang, Angel Zhang, Bryan Chan, Tomasz S. Czajkowski, Yaoqing Gao
2023	—	`conf`	Efficient Data Streaming for a Tightly-Coupled Coarse-Grained Reconfigurable Array. IPDPS Workshops Mahdi Abbaszadeh, Tarek S. Abdelrahman, Reza Azimi, Tomasz S. Czajkowski, Maziar Goudarzi
2018	A	`conf`	High-level synthesis of software-customizable floating-point cores. DATE Samridhi Bansal, Hsuan Hsiao, Tomasz S. Czajkowski, Jason Helge Anderson
2018	Misc	`conf`	Modeling and Rendering of Volumetric Clouds in Real-Time with Unreal Engine 4. ICCVG Lukasz Nowak, Artur Bak, Tomasz S. Czajkowski, Konrad Wojciechowski
2018	Misc	`conf`	Real-Time Simulation of Animated Characters Crowd in Unreal Engine 4. ICCVG Michal Rosenbeiger, Artur Bak, Tomasz S. Czajkowski
2015	A	`conf`	High-Level Design Tools for Floating Point FPGAs. FPGA Deshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski
2015	A	`conf`	Silicon Verification using High-Level Design Tools (Abstract Only). FPGA Tomasz S. Czajkowski
2014	C	`conf`	Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. EUC Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson
2013	Misc	`conf`	From software to accelerators with LegUp high-level synthesis. CASES Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson
2013	A	`conf`	Harnessing the power of FPGAs using altera's OpenCL compiler. FPGA Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling
2013	J	`jnl`	LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. ACM Trans. Embed. Comput. Syst. Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson
2012	B	`conf`	From opencl to high-performance hardware on FPGAS. FPL Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh
2012	Misc	`conf`	Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. FCCM Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Brown, Tomasz S. Czajkowski
2012	A	`conf`	Impact of FPGA architecture on resource sharing in high-level synthesis. FPGA Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Brown, Tomasz S. Czajkowski
2011	A	`conf`	LegUp: high-level synthesis for FPGA-based processor/accelerator systems. FPGA Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Brown, Tomasz S. Czajkowski
2010	J	`jnl`	Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tomasz S. Czajkowski, Stephen Dean Brown
2008	B	`conf`	Fast toggle rate computation for FPGA circuits. FPL Tomasz S. Czajkowski, Stephen Dean Brown
2008	J	`jnl`	Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tomasz S. Czajkowski, Stephen Dean Brown
2008	A*	`conf`	Functionally linear decomposition and synthesis of logic circuits for FPGAs. DAC Tomasz S. Czajkowski, Stephen Dean Brown
2007	A*	`conf`	Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. DAC Tomasz S. Czajkowski, Stephen Dean Brown
2004	A	`conf`	A synthesis oriented omniscient manual editor. FPGA Tomasz S. Czajkowski, Jonathan Rose