Tomasz Garbolino

17 papers B 2C 8Misc 1Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2014 C conf
Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections.
DDECS
Tomasz Garbolino
2011 B conf
Optimal on-line built-in self-test structure for system-reliability improvement.
IEEE Congress on Evolutionary Computation
Gregor Papa, Tomasz Garbolino
2010 J jnl
Genetic algorithm for test pattern generator design - Automatic evolution of circuits.
Appl. Intell.
Tomasz Garbolino, Gregor Papa
2010 C conf
How to reduce size of a signature-based diagnostic dictionary used for testing of connections.
DDECS
Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
2010 — conf
Reduced-size signature-based diagnostic dictionary for interconnection testing.
PDeS
Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
2009 C conf
Effective BIST for crosstalk faults in interconnects.
DDECS
Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
2008 — conf
Deterministic Test Pattern Generator Design.
EvoWorkshops
Gregor Papa, Tomasz Garbolino, Franc Novak
2008 C conf
Interconnect Faults Identification and Localization Using Modified Ring LFSRs.
DDECS
Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec
2008 C conf
Test Pattern Generator Design Optimization Based on Genetic Algorithm.
IEA/AIE
Tomasz Garbolino, Gregor Papa
2007 C conf
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing.
DDECS
Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka
2007 C ed.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007
DDECS
Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino
2006 C conf
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor.
DDECS
Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka
2006 B conf
Test-per-Clock Detection, Localization and Identification of Interconnect Faults.
ETS
Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
2004 J jnl
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.
J. Electron. Test.
Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa
2002 J jnl
Efficient test pattern generators based on specific cellular automata structures.
Microelectron. Reliab.
Tomasz Garbolino, Andrzej Hlawiczka
2000 — conf
Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path.
ETW
Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof
1999 Misc conf
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits.
EDCC
Tomasz Garbolino, Andrzej Hlawiczka