Tom Waayers

14 papers A 8C 1Journal 2Unranked 3
YearRankTypeTitle / Venue / Authors
2013 C conf
Industrial Application of IEEE P1687 for an Automotive Product.
DSD
Martin Keim, Tom Waayers, Richard Morren, Friedrich Hapke, Rene Krenz-Baath
2010 A conf
Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains.
ITC
Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab
2005 A conf
Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain.
ITC
Tom Waayers, Richard Morren, Roberto Grandi
2005 — conf
IEEE Std 1500 Compliant Infrastructure forModular SOC Testing.
Asian Test Symposium
Tom Waayers, Erik Jan Marinissen, Maurice Lousberg
2004 A conf
Extending the Digital Core-based Test Methodology to Support Mixed-Signal.
ITC
Geert Seuren, Tom Waayers
2004 — conf
Infrastructure for modular SOC testing.
CICC
Erik Jan Marinissen, Tom Waayers
2003 A conf
An extension to JTAG for at-speed debug on a system.
ITC
Leon van de Logt, Frank van der Heyden, Tom Waayers
2003 A conf
An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips.
ITC
Tom Waayers
2003 J jnl
Multi-TAP Controller Architecture for Digital System Chips.
J. Electron. Test.
Bart Vermeulen, Tom Waayers, Sjaak Bakker
2002 A conf
Core-Based Scan Architecture for Silicon Debug.
ITC
Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel
2002 A conf
EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.
ITC
Bart Vermeulen, Tom Waayers, Sjaak Bakker
2002 J jnl
Enhanced Reduced Pin-Count Test for Full-Scan Design.
J. Electron. Test.
Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier
2001 — conf
A P1500 Compliant Programable BistShell for Embedded Memories.
MTDT
Sandeep Koranne, Tom Waayers, Robert Beurze, Clemens Wouters, Sunil Kumar, G. S. Visweswara
2001 A conf
Enhanced reduced pin-count test for full-scan design.
ITC
Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier