Tom Eeckelaert

14 papers A* 2A 4Journal 3Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 0.67-5.67-GHz Ring-Based MDLL With 154-fs RMS Jitter and Stochastic Sampling for Spurious Tone Reduction in 5-nm FinFET.
IEEE Trans. Very Large Scale Integr. Syst.
Jared Mercier, Dirk Pfaff, Robert Abbott, Tom Eeckelaert, Ralph Mason
2025 J jnl
A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS.
IEEE J. Solid State Circuits
Dirk Pfaff, Muhammad Nummer, Noman Hai, Jingjing Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Choon-Haw C. H. Leong, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri, David A. Yokoyama-Martin
2025 — conf
A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited).
CICC
Dirk Pfaff, Muhammad Nummer, Noman Hai, Jingjing Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Choon-Haw CH Leong, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Tahseen Shakir, Carlos Carvalho, Howard Huang, Ralph Mason, Fahmida Brishty, Ifrah Jaffri, David A. Yokoyama-Martin
2024 — conf
7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS.
ISSCC
Dirk Pfaff, Muhammad Nummer, Noman Hai, Peter Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Shahab Moazzeni, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri
2007 A conf
An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection.
DATE
Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
2007 — conf
Automated synthesis of complex analog circuits.
ECCTD
Georges G. E. Gielen, Tom Eeckelaert, Ewout Martens, Trent McConaghy
2007 J jnl
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming
CoRR
Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen
2006 — conf
A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology.
ICECS
Raf Schoofs, Tom Eeckelaert, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
2006 A* conf
Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard.
DAC
Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
2005 A conf
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming.
DATE
Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen
2005 — conf
CAFFEINE: template-free symbolic model generation of analog circuits via canonical form functions and genetic programming.
ESSCIRC
Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen
2005 A conf
Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces.
DATE
Tom Eeckelaert, Trent McConaghy, Georges G. E. Gielen
2005 A* conf
Performance space modeling for hierarchical synthesis of analog integrated circuits.
DAC
Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert
2003 A conf
Generalized Posynomial Performance Modeling.
DATE
Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen