Tom Chen - RankMe

90 papers A 10B 1C 10Misc 2Journal 25Unranked 42

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	A handheld electrochemical sensing platform for point-of-care diagnostic applications. BioCAS Lang Yang, Tom Chen
2016	—	`conf`	A 0.2 nJ/bit QPSK transmitter with tuning for process variation for biomedical telemetry in the MedRadio band of 401-457 MHz. MWSCAS Abhiram Reddy Gundla, Tom Chen
2016	—	`conf`	A compact signal generation and acquisition circuit for electrochemical impedance spectroscopy. BioCAS Lang Yang, Tom Chen
2016	J	`jnl`	A novel high-throughput method for table look-up based analog design automation. Integr. Yishai Statter, Tom Chen
2016	J	`jnl`	A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis. Microprocess. Microsystems Mozammel Hossain, John Badar, Jack DiLullo, Tom Chen
2016	C	`conf`	An efficient multi channel, 425µW QPSK transmitter with tuning for process variation in the Medical Implantable Communications Service (MICS) band of 402-405MHz. VLSI-SoC Abhiram Reddy Gundla, Tom Chen
2016	—	`conf`	Design of an integrated microelectrode array system for high spatiotemporal resolution chemical imaging. BioCAS William Tedjo, Rachel Feeny, Chad Eitel, Luke Schwerdtfeger, Stacy Willett, Charles Henry, Stuart Tobet, Tom Chen
2016	J	`jnl`	Γ (Gamma): A SaaS-enabled fast and accurate analog design System. Integr. Yishai Statter, Tom Chen
2015	—	`conf`	A low power frequency synthesizer for biosensor applications in the MedRadio band. MWSCAS Abhiram Reddy Gundla, Tom Chen
2015	J	`jnl`	Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design. Integr. Mozammel Hossain, Chirag Desai, Tom Chen, Vikas Agarwal
2014	—	`conf`	A CMOS Temperature Sensor with -0.34°C to 0.27°C Inaccuracy from -30°C to 80°C. ISVLSI Hai Chi, Tom Chen
2014	—	`conf`	Design of a 50MΩ Transimpedance Amplifier with 0.98fa/vHz Input Inferred Noise in a 0.18µM CMOS Technology. BIODEVICES William Wilson, Tom Chen
2013	—	`conf`	A 0.18µm CMOS 2nd Order Sigma-Delta Modulator for Low-power Biosensor Applications. BIODEVICES Ryan Selby, Tom Chen
2013	—	`conf`	A 0.18µm CMOS switched-capacitor amplifier using current-starving inverter based op-amp for low-power biosensor applications. LASCAS Ryan Selby, Kern Tucker, William Wilson, Tom Chen
2013	—	`conf`	A 2nd Order CMOS Sigma-Delta Modulator Design Suitable for Low-Power Biosensor Applications. BIOSTEC (Selected Papers) Ryan Selby, Tom Chen
2013	C	`conf`	A Low Power 15-Bit Decimator in 0.18um CMOS for Biomedical Applications. DSD Kristin Scholfield, Tom Chen
2013	—	`conf`	A current-starved inverter-based differential amplifier design for ultra-low power applications. LASCAS William Wilson, Tom Chen, Ryan Selby
2010	—	`conf`	Fast Evaluation of Analog Circuits Using Linear Programming. ISVLSI Zach Cashero, Allen Chen, Ryan Hoppal, Tom Chen
2010	J	`jnl`	Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery. IEEE Trans. Very Large Scale Integr. Syst. Charles Thangaraj, Robert Pownall, Phil Nikkel, Guangwei Yuan, Kevin L. Lear, Tom Chen
2010	C	`conf`	On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications. DSD Allen Chen, Ryan Hoppal, Tom Chen
2010	—	`conf`	On power and performance tradeoff of L2 cache compression. APCCAS Chandrika Jena, Tim Mason, Tom Chen
2010	J	`jnl`	Rapid design space exploration using legacy design data and technology scaling trend. Integr. Charles Thangaraj, Alkan Cengiz, Tom Chen
2008	C	`conf`	Design target exploration for meeting time-to-market using pareto analysis. ISCAS Charles Thangaraj, Tom Chen
2008	—	`conf`	Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. DELTA Charles Thangaraj, Tom Chen
2007	J	`jnl`	Editorial. Microelectron. J. Daniela De Venuto, Tom Chen
2007	—	`conf`	Power andPerformance Analysis for Early Design Space Exploration. ISVLSI Charles Thangaraj, Tom Chen
2006	Misc	`conf`	Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. VLSI Design Jayashree Sridharan, Tom Chen
2006	A	`conf`	Modeling multiple input switching of CMOS gates in DSM technology using HDMR. DATE Jayashree Sridharan, Tom Chen
2005	J	`jnl`	A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Medha Kulkarni, Tom Chen
2005	J	`jnl`	International Symposium on Quality Electronic Design. Microelectron. J. Daniela De Venuto, Tom Chen
2005	A	`conf`	Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions. DATE Ajith Chandy, Tom Chen
2005	C	`conf`	Stability analysis of active clock deskewing systems using a control theoretic approach. ACC Vinil Varghese, Tom Chen, Peter Michael Young
2005	—	`conf`	Stability analysis of active clock deskewing systems using a control theoretic approach. ASP-DAC Vinil Varghese, Tom Chen, Peter Michael Young
2005	A	`conf`	Systematic Analysis of Active Clock Deskewing Systems Using Control Theory. DATE Vinil Varghese, Tom Chen, Peter Michael Young
2004	—	`conf`	A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects. ISQED Medha Kulkarni, Tom Chen
2004	—	`conf`	Design of CMOS IO Drivers with Less Sensitivity to Process, Voltage, and Temperature Variations. DELTA Gerald Esch Jr., Tom Chen
2004	J	`jnl`	Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations. IEEE Trans. Very Large Scale Integr. Syst. Gerald Esch Jr., Tom Chen
2004	—	`conf`	RUBASTEM: A Method for Testing VHDL Behavioral Models. HASE Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen
2004	J	`jnl`	Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tom Chen, Amjad Hajjar
2004	J	`jnl`	Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Geun Rae Cho, Tom Chen
2003	C	`conf`	A Rule-Based Software Testing Method for VHDL Models. VLSI-SOC Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen
2003	J	`jnl`	A VLSI architecture for video-object segmentation. IEEE Trans. Circuits Syst. Video Technol. Jinsang Kim, Tom Chen
2003	—	`conf`	Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics. ISQED Tom Chen, Amjad Hajjar
2003	—	`conf`	Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. ISQED Geun Rae Cho, Tom Chen
2003	—	`conf`	Design of a CMOS test chip for package models and I/O characteristics verification. ASP-DAC Chetan Despande, Tom Chen
2003	Misc	`conf`	On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. VLSI Design Geun Rae Cho, Tom Chen
2002	—	`conf`	An Accurate Coverage Forecasting Model for Behavioral Model Verification. DELTA Amjad Hajjar, Tom Chen
2002	—	`conf`	Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power Applications. SEAL Geun Rae Cho, Tom Chen
2002	J	`jnl`	Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification. J. Electron. Test. Tom Chen, Andre Bai, Amjad Hajjar, Anneliese Amschler Andrews, Charles Anderson
2002	—	`conf`	Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria. ISQED Amjad Hajjar, Tom Chen
2002	—	`conf`	Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. ISQED Geun Rae Cho, Tom Chen
2002	C	`conf`	On The Impact of Technology Scaling On Mixed PTL/Static Circuits. ICCD Geun Rae Cho, Tom Chen
2002	—	`conf`	On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS Geun Rae Cho, Tom Chen
2001	A	`conf`	High quality behavioral verification using statistical stopping criteria. DATE Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman
2001	—	`conf`	Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. ISQED Tom Chen
2001	J	`jnl`	Multiple feature clustering for image sequence segmentation. Pattern Recognit. Lett. Jinsang Kim, Tom Chen
2001	J	`jnl`	On Mixed PTL/Static Logic for Low-power and High-speed Circuits. VLSI Design Geun Rae Cho, Tom Chen
2001	A	`conf`	On the impact of on-chip inductance on signal nets under the influence of power grid noise. DATE Tom Chen
2001	—	`conf`	Real-time Video Objects Segmentation using a Highly Pipelined Microarchitecture. VIIP Jinsang Kim, Tom Chen
2001	—	`conf`	Stopping Criteria Comparison: Towards High Quality Behavioral Verification. ISQED Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman
2000	—	`conf`	A VLSI Architecture for Image Sequence Segmentation using Edge Fusion. CAMP Jinsang Kim, Tom Chen
2000	—	`conf`	Achieving the Quality of Verification for Behavioral Models with Minimum Effort. ISQED Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu
2000	—	`conf`	On choosing test criteria for behavioral level hardware design verification. HLDVT Anneliese von Mayrhauser, Tom Chen, Jan Kok, Chuck Anderson, Anita Read, Amjad Hajjar
2000	—	`conf`	On statistical behavior of branch coverage in testing behavioral VHDL models. HLDVT Amjad Hajjar, Tom Chen, Anneliese von Mayrhauser
2000	B	`conf`	Segmentation of Image Sequences Using SOFM Networks. ICPR Jinsang Kim, Tom Chen
1999	—	`conf`	Assessing Defect Coverage of Memory Testing Algorithms. Great Lakes Symposium on VLSI Von-Kyoung Kim, Tom Chen
1999	J	`jnl`	COBRA: a 100-MOPS single-chip programmable and expandable FFT. IEEE Trans. Very Large Scale Integr. Syst. Tom Chen, Glen Sunada, Jain Jin
1999	—	`conf`	Efficient Verification of Behavioral Models Using Sequential Sampling Technique. VLSI Tom Chen, Isabelle Munn, Anneliese von Mayrhauser, Amjad Hajjar
1999	—	`conf`	Fault Coverage Estimation for Early Stage of VLSI Design. Great Lakes Symposium on VLSI Von-Kyoung Kim, Tom Chen, Mick Tegethoff
1999	—	`conf`	How Much Testing is Enough? Applying Stopping Rules to Behavioral Model Testing. HASE Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu
1999	J	`jnl`	On comparing functional fault coverage and defect coverage for memory testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Von-Kyoung Kim, Tom Chen
1999	J	`jnl`	VLSI Architecture for Real-Time Edge Linking. IEEE Trans. Pattern Anal. Mach. Intell. Amjad Hajjar, Tom Chen
1998	—	`conf`	Fast Antirandom (FAR) Test Generation. HASE Anneliese von Mayrhauser, Andre Bai, Tom Chen, Charles Anderson, Amjad Hajjar
1997	J	`jnl`	A Real-Time Edge Detector: Algorithm and VLSI Architecture. Real Time Imaging Fahad M. Alzahrani, Tom Chen
1997	—	`conf`	A real-time high performance edge detector for computer vision applications. ASP-DAC Fahad M. Alzahrani, Tom Chen
1997	A	`conf`	ASIC Manufacturing Test Cost Prediction at Early Design Stage. ITC Von-Kyoung Kim, Tom Chen, Mick Tegethoff
1997	J	`jnl`	Simulation Techniques for the Manufacturing Test of MCMs. J. Electron. Test. Mick Tegethoff, Tom Chen
1996	A	`conf`	ASIC Yield Estimation at Early Design Cycle. ITC Von-Kyoung Kim, Mick Tegethoff, Tom Chen
1996	—	`conf`	Assessing Neural Networks as Guides for Testing Activities. IEEE METRICS Charles Anderson, Anneliese von Mayrhauser, Tom Chen
1996	J	`jnl`	Sensitivity Analysis of Critical Parameters in Board Test. IEEE Des. Test Comput. Mick Tegethoff, Tom Chen
1995	J	`jnl`	Performance and Area Optimization of VLSI Systems Using Genetic Algorithms. VLSI Design Xiao-Dong Wang, Tom Chen
1994	C	`conf`	COBRA: An 1.2 Million Transistor Expandable Column FFT Chip. ICCD Glen Sunada, Jain Jin, Matt Berzins, Tom Chen
1994	A	`conf`	Defects, Fault Coverage, Yield and Cost in Board Manufacturing. ITC Mick Tegethoff, Tom Chen
1994	A	`conf`	Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs. ITC Mick Tegethoff, Tom Chen
1994	C	`conf`	On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems. ICCD Fahad M. Alzahrani, Tom Chen
1993	J	`jnl`	An expandable column fft architecture using circuit switching networks. J. VLSI Signal Process. Tom Chen, Li Zhu
1993	J	`jnl`	Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips. IEEE Trans. Very Large Scale Integr. Syst. Tom Chen, Glen Sunada
1992	A	`conf`	A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories. ITC Tom Chen, Glen Sunada
1992	C	`conf`	An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing. ICCD Tom Chen, Glen Sunada
1991	—	`conf`	A Fast 1024-Point FFT Architecture. ICPP (1) Tom Chen, Li Zhu