Tohru Sasaki

17 papers A* 4A 2B 2Journal 7Unranked 2
YearRankTypeTitle / Venue / Authors
2021 J jnl
Surrounding Structure Estimation Using Ambient Light.
Int. J. Autom. Technol.
Bilal Ahmed Mir, Tohru Sasaki, Yusuke Nagahata, Eri Yamabe, Naoya Miwa, Kenji Terabayashi
2020 J jnl
Hydraulic Micro Device with Force Sensing for Measurement of Mechanical Characteristics.
Int. J. Autom. Technol.
Tohru Sasaki, Yudai Fujiwara, Kaoru Tachikawa, Kenji Terabayashi, Kuniaki Dohda
2020 J jnl
Network Connectivity Control of Mobile Robots by Fast Position Estimations and Laplacian Kernel.
J. Robotics Mechatronics
Yusuke Ikemoto, Kenichiro Nishimura, Yuichiro Mizutama, Tohru Sasaki, Mitsuru Jindai
2019 B conf
Hug Behavior Request Model with Approaching Human for Hug Robots.
ICSR
Mitsuru Jindai, Shunsuke Ota, Toshiyuki Yasuda, Tohru Sasaki
2018 J jnl
Position and Posture Measurement Method of the Omnidirectional Camera Using Identification Markers.
J. Robotics Mechatronics
Naoya Hatakeyama, Tohru Sasaki, Kenji Terabayashi, Masahiro Funato, Mitsuru Jindai
2017 B conf
Development of a hug request motion model during active approach to human.
SMC
Mitsuru Jindai, Shunsuke Ota, Toshiyuki Yasuda, Tohru Sasaki, Yoshihiro Sejima
2015 — conf
Handshake request motion model with an approaching human for a handshake robot system.
RAM/CIS
Mitsuru Jindai, Shunsuke Ota, Yusuke Ikemoto, Tohru Sasaki
2015 — conf
Handshake response motion model with approaching of human based on an analysis of human handshake motions.
ICUMT
Shunsuke Ota, Mitsuru Jindai, Tohru Sasaki, Yusuke Ikemoto
2008 J jnl
Motion Characteristics of Loop Type Elliptic Resonator.
J. Robotics Mechatronics
Tohru Sasaki, Kunio Koizumi, Motofumi Sasaki
1987 J jnl
Block-Level Hardware Logic Simulation Machine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Nobuhiko Koike, Kenji Ohmori
1986 A* conf
HAL II: a mixed level hardware logic simulation system.
DAC
Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Hiroshi Ishikura, Nobuhiko Koike
1985 J jnl
HAL: A High-Speed Logic Simulation Machine.
IEEE Des. Test
Nobuhiko Koike, Kenji Ohmori, Tohru Sasaki
1984 A conf
Logic Design Verification Using Automated Test Generation.
ITC
Tohru Sasaki, Shunichi Kato, Nobuyoshi Nomizu, Hidetoshi Tanaka
1983 A conf
A High Level Test Pattern Generation Algorithm.
ITC
Masato Kawai, Hideo Shibano, Shigehiro Funatsu, Shunichi Kato, T. Kurobe, K. Ookawa, Tohru Sasaki
1983 A* conf
HAL: A block level HArdware Logic simulator.
DAC
Tohru Sasaki, Nobuhiko Koike, Kenji Ohmori, Kyoji Tomita
1981 A* conf
Hierarchical design verification for large digital systems.
DAC
Tohru Sasaki, Akihiko Yamada, Toshinori Aoyama, Katsutoshi Hasegawa, Shunichi Kato, Shinichi Sato
1980 A* conf
MIXS: A mixed level simulator for large digital system logic verification.
DAC
Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu