Tohru Mogami

14 papers C 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication.
IEEE Trans. Very Large Scale Integr. Syst.
Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Hideharu Amano, Tohru Mogami, Yoshio Mita, Makoto Ikeda, Tadahiro Kuroda
2025 C conf
An SoC Design and Fabrication Hands-On Educational Course within One Week Using Structured ASIC.
ISCAS
Hideharu Amano, Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Tohru Mogami, Yoshio Mita, Makoto Ikeda
2025 — conf
Can the Agile-Chip Platform Carve Out a Niche Between ASICs and FPGAs?
COOL CHIPS
Hideharu Amano, Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Tohru Mogami, Yoshio Mita, Makoto Ikeda
2018 — conf
Spectral variation analysis of integrated silicon photonics devices by using optical wafer probing.
ICICDT
Tsuyoshi Horikawa, Tohru Mogami
2017 — conf
High-performance silicon photonics platform for low-power photonic integrated circuits.
MIXDES
Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
2017 — conf
Resonant Wavelength Variation Modelling for Microring Resonators based on Fabrication Deviation Analysis.
ECOC
Tsuyoshi Horikawa, Daisuke Shimura, Hiroyuki Takahashi, Jun Ushida, Yohei Sobu, Akemi Shiina, Masatoshi Tokushima, Seok-Hwan Jeong, Keizo Kinoshita, Tohru Mogami
2013 J jnl
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation.
IEICE Trans. Electron.
Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2012 — conf
HiSIM-RP: A reverse-profiling based 1
ISQED
Hironori Sakamoto, Shigetaka Kumashiro, Shigeo Sato, Naoki Wakita, Tohru Mogami
2012 J jnl
On-Chip In-Place Measurements of V
IEICE Trans. Electron.
Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011 J jnl
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits.
IEICE Trans. Electron.
Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011 — conf
Accurate analysis of substrate sensitivity of active transistors in an analog circuit.
ISQED
Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011 J jnl
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement.
IEICE Trans. Electron.
Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2003 J jnl
A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC.
IEEE J. Solid State Circuits
Akira Tanabe, Yasushi Nakahara, Akio Furukawa, Tohru Mogami
1997 J jnl
A 0.25-μm CMOS 0.9-V 100-MHz DSP core.
IEEE J. Solid State Circuits
Masanori Izumikawa, Hiroyuki Igura, Hitoshi Wakabayashi, Ken Nakajima, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina