Tohru Ishihara

124 papers A* 1A 14B 1C 4Misc 1Journal 44Unranked 59

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Cross-Layer Approximate Computing and Critical Path Isolation for Energy-Efficient and Variation-Tolerant Design. MCSoC Meisei Yamaguchi, Yutaka Masuda, Tohru Ishihara
2025	J	`jnl`	Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. Tohru Ishihara
2025	J	`jnl`	Optoelectronic Pipeline Architecture of Convolutional RNN for Energy Efficient Inference at the Speed of Light. IEICE Trans. Electron. Chunlu Wang, Yutaka Masuda, Tohru Ishihara
2025	—	`conf`	Panel Discussions: "Sustainable AI: Emerging Architectures, Devices, and Quantum Computing Towards Future Computing". COOL CHIPS Tohru Ishihara, Jangwoo Kim, Kazutoshi Kobayashi, Jose Martinez
2025	—	`conf`	Piecewise-Linear Approximation of Self-Attention and Its Accuracy-Aware Training for Area-Efficient Vision Transformer Inference Accelerator. ISQED Teppei Kawamura, Yutaka Masuda, Tohru Ishihara
2025	—	`conf`	Utilizing Wide Range Energy/Delay Tradeoffs in Logarithmic Multipliers to Reduce Energy Dissipated for AI Inference Workloads. MCSoC Tai-Feng Chen, Yutaka Masuda, Tohru Ishihara
2024	J	`jnl`	Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
2024	J	`jnl`	Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. Tohru Ishihara
2024	J	`jnl`	Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takumi Komori, Yutaka Masuda, Tohru Ishihara
2023	—	`conf`	A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design. SOCC Tai-Feng Chen, Yutaka Masuda, Tohru Ishihara
2023	J	`jnl`	An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Lingxiao Hou, Yutaka Masuda, Tohru Ishihara
2023	A	`conf`	An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits. DATE Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
2023	J	`jnl`	Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yutaka Masuda, Yusei Honda, Tohru Ishihara
2023	C	`conf`	Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design. IOLTS Yusei Honda, Yutaka Masuda, Tohru Ishihara
2022	—	`conf`	An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers. ASP-DAC Lingxiao Hou, Yutaka Masuda, Tohru Ishihara
2022	J	`jnl`	Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
2022	B	`conf`	DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms. RTCSA Takumi Komori, Yutaka Masuda, Tohru Ishihara
2022	—	`conf`	Energy efficient OEO conversion and its applications to photonic integrated systems. OFC Akihiko Shinya, Kengo Nozaki, Shota Kita, Tohru Ishihara, Shinji Matsuo, Masaya Notomi
2022	J	`jnl`	Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yutaka Masuda, Jun Nagayama, Taiyu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
2022	—	`conf`	Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks. ISVLSI Taisei Ichikawa, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
2022	A*	`conf`	Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. DAC Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
2022	—	`conf`	Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. SOCC Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera
2021	J	`jnl`	A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2021	A	`conf`	Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. DATE Yutaka Masuda, Jun Nagayama, Taiyu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
2021	C	`conf`	Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing. IOLTS Kazuki Yoshisue, Yutaka Masuda, Tohru Ishihara
2021	—	`conf`	Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. ISQED Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
2021	J	`jnl`	Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Naoki Hattori, Jun Shiomi, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
2020	—	`conf`	A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. ISVLSI Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2020	—	`conf`	An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. ICRC Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2020	—	`conf`	Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. ISVLSI Khyati Kiyawat, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
2019	J	`jnl`	A Design Method of a Cell-Based Amplifier for Body Bias Generation. IEICE Trans. Electron. Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2019	—	`conf`	An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. PHOTONICS@SC Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi
2019	J	`jnl`	Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. Integr. Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2019	—	`conf`	BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. ASP-DAC Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2019	J	`jnl`	Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2019	J	`jnl`	On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2018	J	`jnl`	An Integrated Nanophotonic Parallel Adder. ACM J. Emerg. Technol. Comput. Syst. Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi
2018	—	`conf`	An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. ICRC Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2018	C	`conf`	Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation. IOLTS Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera
2018	—	`conf`	Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. PATMOS Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2018	J	`jnl`	Minimum Energy Point Tracking with All-Digital On-Chip Sensors. J. Low Power Electron. Jun Shiomi, Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
2018	—	`conf`	Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics. ICRC Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi
2018	—	`conf`	Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization. SoCC Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera
2017	J	`jnl`	A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
2017	J	`jnl`	A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2017	—	`conf`	On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator. VLSI-DAT Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera
2016	—	`conf`	A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. ASP-DAC Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2016	—	`conf`	An integrated optical parallel adder as a first step towards light speed data processing. ISOCC Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi
2016	J	`jnl`	Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2016	—	`conf`	Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. PATMOS Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2016	—	`conf`	Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing. SoCC Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
2016	—	`conf`	Variability- and correlation-aware logical effort for near-threshold circuit design. ISQED Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015	—	`conf`	An energy-efficient on-chip memory structure for variability-aware near-threshold operation. ISQED Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015	—	`conf`	An impact of process variation on supply voltage dependence of logic path delay variation. VLSI-DAT Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2015	—	`conf`	Energy reduction by built-in body biasing with single supply voltage operation. ISQED Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera
2015	J	`jnl`	Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. IPSJ Trans. Syst. LSI Des. Methodol. Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2015	—	`conf`	Microarchitectural-level statistical timing models for near-threshold circuit design. ASP-DAC Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015	J	`jnl`	Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015	J	`jnl`	Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. IEEE J. Solid State Circuits Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2014	J	`jnl`	An Integrated Framework for Energy Optimization of Embedded Real-Time Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada
2014	—	`conf`	Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. SoCC Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2014	—	`conf`	Variation-aware Flip-Flop energy optimization for ultra low voltage operation. SoCC Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2014	—	`conf`	Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring. A-SSCC Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2013	—	`conf`	Analysis and comparison of XOR cell structures for low voltage circuit design. ISQED Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2013	J	`jnl`	DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kyungsoo Lee, Tohru Ishihara
2013	J	`jnl`	DLIC: Decoded loop instructions caching for energy-aware embedded processors. ACM Trans. Embed. Comput. Syst. Ji Gu, Hui Guo, Tohru Ishihara
2013	J	`jnl`	Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2012	—	`conf`	A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems. SMARTGREENS Ji Gu, Tohru Ishihara
2012	—	`conf`	A Dynamic Reconfiguration Technique for PV and Capacitor Arrays to Improve the Efficiency in Energy Harvesting Embedded Systems. SMARTGREENS Kyungsoo Lee, Tohru Ishihara
2012	—	`conf`	A Standard Cell Optimization Method for Near-Threshold Voltage Operations. PATMOS Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2012	C	`conf`	A flexible structure of standard cell and its optimization method for near-threshold voltage operation. ICCD Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2012	—	`conf`	I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays. ESTIMedia Kyungsoo Lee, Tohru Ishihara
2012	—	`conf`	Loop instruction caching for energy-efficient embedded multitasking processors. ESTIMedia Ji Gu, Tohru Ishihara, Kyungsoo Lee
2012	J	`jnl`	Processor Energy Characterization for Compiler-Assisted Software Energy Reduction. J. Electr. Comput. Eng. Lovic Gauthier, Tohru Ishihara
2011	A	`conf`	An integrated optimization framework for reducing the energy consumption of embedded real-time applications. ISLPED Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada
2011	A	`conf`	Developing an integrated verification and debug methodology. DATE Akitoshi Matsuda, Tohru Ishihara
2011	J	`jnl`	Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Lovic Gauthier, Tohru Ishihara
2011	J	`jnl`	Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies. Trans. High Perform. Embed. Archit. Compil. Maziar Goudarzi, Tohru Ishihara, Hamid Noori
2011	—	`conf`	Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits. PATMOS Takumi Okuhira, Tohru Ishihara
2010	J	`jnl`	A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tohru Ishihara
2010	—	`conf`	An RTOS in hardware for energy efficient software-based TCP/IP processing. SASP Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura
2010	J	`jnl`	Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. J. Signal Process. Syst. Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
2010	Misc	`conf`	Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems. CASES Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada
2010	J	`jnl`	SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation. IEEE Trans. Very Large Scale Integr. Syst. Maziar Goudarzi, Tohru Ishihara
2009	J	`jnl`	An Optimization Technique for Low-Energy Embedded Memory Systems. IPSJ Trans. Syst. LSI Des. Methodol. Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
2009	—	`conf`	Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories. ESTIMedia Lovic Gauthier, Tohru Ishihara
2009	J	`jnl`	Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion. IPSJ Trans. Syst. LSI Des. Methodol. Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
2008	—	`conf`	A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. EUC (1) Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Tohru Ishihara
2008	J	`jnl`	A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V Microelectron. J. Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
2008	—	`conf`	AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato
2008	—	`conf`	Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura
2008	—	`conf`	Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. ISVLSI Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara
2008	—	`conf`	Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. ACM Great Lakes Symposium on VLSI Maziar Goudarzi, Tohru Ishihara
2008	J	`jnl`	Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. IEICE Trans. Electron. Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
2008	A	`conf`	Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation. ISLPED Maziar Goudarzi, Tohru Ishihara
2008	—	`conf`	Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
2008	J	`jnl`	Value-dependence of SRAM leakage in deca-nanometer technologies. IEICE Electron. Express Maziar Goudarzi, Tohru Ishihara
2008	—	`conf`	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. HiPEAC Maziar Goudarzi, Tohru Ishihara, Hamid Noori
2008	J	`jnl`	Way-Scaling to Reduce Power of Cache with Delay Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara
2007	—	`conf`	A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
2007	J	`jnl`	A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors CoRR Tohru Ishihara, Farzan Fallah
2007	J	`jnl`	Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. IEICE Trans. Electron. Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
2007	—	`conf`	Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTIMedia Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
2007	A	`conf`	Task scheduling for reliable cache architectures of multiprocessor systems. DATE Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
2006	—	`conf`	A Simulation-Based Soft Error Estimation Methodology for Computer Systems. ISQED Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto
2006	—	`conf`	An Energy Characterization Framework for Software-Based Embedded Systems. ESTIMedia Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah
2005	A	`conf`	A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. DATE Tohru Ishihara, Farzan Fallah
2005	A	`conf`	A cache-defect-aware code placement algorithm for improving the performance of processors. ICCAD Tohru Ishihara, Farzan Fallah
2005	A	`conf`	A non-uniform cache architecture for low power system design. ISLPED Tohru Ishihara, Farzan Fallah
2005	—	`conf`	Energy-Efficient Embedded System Design at 90nm and Below - A System-Level Perspective -. ISHPC Tohru Ishihara
2003	—	`conf`	Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada
2002	—	`conf`	A Power Minimization Technique for Arithmetic Circuits by Cell Selection. ASP-DAC/VLSI Design Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
2002	—	`conf`	An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. ASP-DAC/VLSI Design Tohru Ishihara, Kunihiro Asada
2001	—	`conf`	A system level memory power optimization technique using multiple supply and threshold voltages. ASP-DAC Tohru Ishihara, Kunihiro Asada
2001	J	`jnl`	Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Des. Test Comput. Takanori Okuma, Hiroto Yasuura, Tohru Ishihara
2000	A	`conf`	A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. DATE Tohru Ishihara, Hiroto Yasuura
2000	J	`jnl`	Flexible System LSI for Embedded Systems and Its Optimization Techniques. Des. Autom. Embed. Syst. Akihiko Inoue, Tohru Ishihara, Hiroto Yasuura
1999	—	`conf`	Real-Time Task Scheduling for a Variable Voltage Processor. ISSS Takanori Okuma, Tohru Ishihara, Hiroto Yasuura
1999	A	`conf`	Way-predicting set-associative cache for high performance and low energy consumption. ISLPED Koji Inoue, Tohru Ishihara, Kazuaki J. Murakami
1998	A	`conf`	Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura
1998	—	`conf`	Power-Pro: Programmable Power Management Architecture. ASP-DAC Tohru Ishihara, Hiroto Yasuura
1998	A	`conf`	Voltage scheduling problem for dynamically variable voltage processors. ISLPED Tohru Ishihara, Hiroto Yasuura
1996	A	`conf`	Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. ISLPED Tohru Ishihara, Hiroto Yasuura
1993	J	`jnl`	On the big Mu in the affine scaling algorithm. Math. Program. Tohru Ishihara, Masakazu Kojima