Tobias Strauch

24 papers A 1B 1C 8Journal 10Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Transaction Level Hierarchy Guided and Functional Coverage Driven Deductive Formal Verification. CoRR Tobias Strauch
2024	A	`conf`	Deductive Formal Verification of Synthesizable, Transaction-Level Hardware Designs Using Coq. DATE Tobias Strauch
2024	C	`conf`	Non-interfering On-line and In-field SoC Testing. RSP Tobias Strauch
2024	J	`jnl`	Non-interfering On-line and In-field SoC Testing. CoRR Tobias Strauch
2024	C	`conf`	Transaction Level Hierarchy Guided and Functional Coverage Driven Deductive Formal Verification. RSP Tobias Strauch
2023	C	`conf`	MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven Prototyping. RSP Tobias Strauch
2019	C	`conf`	An RTL ATPG Flow Using the Gate Inherent Fault (GIF) Model Applied on Non-, Standard- and Random-Access-Scan (RAS). DSD Tobias Strauch
2019	C	`conf`	Combining Simulation and FPGA Based Verification to an Affordable and Ultra-Fast Multi-Billion-Gate Verification System. RSP Tobias Strauch
2018	J	`jnl`	Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++. CoRR Tobias Strauch
2018	C	`conf`	Dynamic Inside-Out Verification Using Inverse Transactions in TLM. FDL Tobias Strauch
2018	J	`jnl`	Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs. CoRR Tobias Strauch
2017	—	`conf`	A Novel RTL ATPG Model Based on Gate Inherent Faults of Complex Gates. MBMV Tobias Strauch
2017	C	`conf`	Acceleration Techniques for System-Hyper-Pipelined Soft-Processors on FPGAs. DSD Tobias Strauch
2017	C	`conf`	An Aspect and Transaction Oriented Programming, Design and Verification Language (PDVL). DSD Tobias Strauch
2017	J	`jnl`	Connecting Things to the IoT by Using Virtual Peripherals on a Dynamically Multithreaded Cortex M3. IEEE Trans. Circuits Syst. I Regul. Pap. Tobias Strauch
2016	J	`jnl`	A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates. CoRR Tobias Strauch
2015	—	`conf`	Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++. MBMV Tobias Strauch
2015	J	`jnl`	Running Identical Threads in C-Slow Retiming based Designs for Functional Failure Detection. CoRR Tobias Strauch
2015	—	`conf`	The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs. ARC Tobias Strauch
2015	J	`jnl`	Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA. CoRR Tobias Strauch
2013	—	`conf`	Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs. PARCO Tobias Strauch
2013	B	`conf`	Timing driven RTL-to-RTL partitioner for multi-FPGA systems. FPL Tobias Strauch
2012	J	`jnl`	Single Cycle Access Structure for Logic Test. IEEE Trans. Very Large Scale Integr. Syst. Tobias Strauch
2011	J	`jnl`	Multi-FPGA System With Unlimited and Self-Timed Wave-Pipelined Multiplexed Routing. IEEE Trans. Very Large Scale Integr. Syst. Tobias Strauch