Tobias Scheipel

14 papers C 5Misc 3Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2025 Misc conf
Formal Modeling and Verification of Low-Level AUTOSAR OS Specifications: Towards Portability and Correctness.
SAC
Vignesh Manjunath, Tobias Scheipel, Marcel Baunach
2025 J jnl
Queryable Microarchitecture Knowledge Base using Retrieval-Augmented Generation.
WiPiEC Journal
Vignesh Manjunath, Jesús Puerta Pestana, Tobias Scheipel, Marcel Baunach
2025 C conf
You Shall Not Stall: Achieving RISC-V On-Demand Runtime-Reconfiguration using SCAIE-V.
DSD
Tobias Scheipel, Maximilian Ogris, Marcel Baunach
2024 Misc conf
Fair and Starvation-Free Spinlock for Real-Time AUTOSAR systems: M-HLP.
SAC
Drona Nagarajan, Tobias Scheipel, Marcel Baunach
2024 Misc conf
Formal Specifications of Real-Time AUTOSAR-Compliant Operating Systems.
RTNS
Drona Nagarajan, Tobias Scheipel, Marcel Baunach
2024 — conf
Stitching FPGA Fabrics with FABulous and OpenLane 2.
CF (Companion)
Leo Moser, Meinhard Kissich, Tobias Scheipel, Marcel Baunach
2024 J jnl
opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs.
WiPiEC Journal
Kristóf Kanics, Meinhard Kissich, Gerhard Wirrer, Tobias Scheipel, Marcel Baunach
2022 C conf
moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems.
DSD
Tobias Scheipel, Florian Angermair, Marcel Baunach
2021 C conf
A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime.
DSD
Tobias Scheipel, Peter Brungs, Marcel Baunach
2020 C conf
FPGA-Based Debugging with Dynamic SignalSelection at Run-Time.
Software Engineering (Workshops)
Gernot Fiala, Tobias Scheipel, Werner Neuwirth, Marcel Baunach
2020 — conf
papagenoX: Generation of Electronics and Logic for Embedded Systems from Application Software.
SENSORNETS
Tobias Scheipel, Marcel Baunach
2018 J jnl
Smart mobility of the future - a challenge for embedded automotive systems.
Elektrotech. Informationstechnik
Marcel Baunach, Renata Martins Gomes, Maja Malenko, Fabian Mauroner, Leandro Batista Ribeiro, Tobias Scheipel
2017 — conf
Einheit zur anwendungsbezogenen Leistungsmessung für die RISC-V-Architektur.
Echtzeit
Tobias Scheipel, Fabian Mauroner, Marcel Baunach
2017 C conf
System-Aware Performance Monitoring Unit for RISC-V Architectures.
DSD
Tobias Scheipel, Fabian Mauroner, Marcel Baunach