Tobias G. Noll

103 papers A* 1A 6B 4C 7Misc 7Journal 24Unranked 53

Year	Rank	Type	Title / Venue / Authors
2018	A	`conf`	Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells. DATE Arne Heittmann, Tobias G. Noll
2017	J	`jnl`	Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup. IEEE Trans. Circuits Syst. II Express Briefs Michael Meixner, Tobias G. Noll
2017	J	`jnl`	Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems. ACM Comput. Surv. Georgia Psychou, Dimitrios Rodopoulos, Mohamed M. Sabry, Tobias Gemmeke, David Atienza, Tobias G. Noll, Francky Catthoor
2017	—	`conf`	Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells. NANOARCH Arne Heittmann, Tobias G. Noll
2017	J	`jnl`	Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency. J. Signal Process. Syst. Martin Broich, Tobias G. Noll
2016	J	`jnl`	A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency. J. Signal Process. Syst. Upasna Vishnoi, Michael Meixner, Tobias G. Noll
2016	—	`conf`	A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects. PATMOS Georgia Psychou, Tobias Gemmeke, Tobias G. Noll
2015	J	`jnl`	Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations. ACM Comput. Surv. Dimitrios Rodopoulos, Georgia Psychou, Mohamed M. Sabry, Francky Catthoor, Antonis Papanikolaou, Dimitrios Soudris, Tobias G. Noll, David Atienza
2015	—	`conf`	Design and synthesis of reconfigurable control-flow structures for CGRA. ReConFig Zoltán Endre Rákossy, Axel Acosta-Aponte, Tobias G. Noll, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay
2015	C	`conf`	On the use of analytical techniques for reliability analysis in presence of hardware-induced errors. INDIN Georgia Psychou, Tobias Gemmeke, Tobias G. Noll
2014	—	`conf`	Limits of gate-level power estimation considering real delay effects and glitches. ISSoC Michael Meixner, Tobias G. Noll
2014	—	`conf`	Optimal data path widths for energy- and area-efficient Max-Log-MAP based LTE Turbo decoders. ISSoC Martin Broich, Tobias G. Noll
2014	Misc	`conf`	Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption. VLSID Michael Meixner, Tobias G. Noll
2014	C	`conf`	Variability analysis of a hybrid CMOS/RS nanoelectronic calibration circuit. ISCAS Arne Heittmann, Tobias G. Noll
2013	—	`conf`	A family of modular area- and energy-efficient QRD-accelerator architectures. ISSoC Upasna Vishnoi, Tobias G. Noll
2013	C	`conf`	An accurate power estimation model for low-power hierarchical-architecture SRAMs. VLSI-SoC Yuan Ren, Tobias G. Noll
2013	—	`conf`	Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays. ACM Great Lakes Symposium on VLSI Qin Wang, Arne Heittmann, Tobias G. Noll
2013	—	`conf`	Cross-layer optimization of QRD accelerators. ESSCIRC Upasna Vishnoi, Tobias G. Noll
2013	A	`conf`	High-level modeling and synthesis for embedded FPGAs. DATE Xiaolin Chen, Shuai Li, Jochen Schleifer, Thomas Coenen, Anupam Chattopadhyay, Gerd Ascheid, Tobias G. Noll
2013	—	`conf`	Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation. ASP-DAC Arne Heittmann, Tobias G. Noll
2013	—	`conf`	Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture SRAMs Based on Accurate Cost Models. VLSI-SoC (Selected Papers) Yuan Ren, Tobias G. Noll
2013	—	`conf`	Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits. ACM Great Lakes Symposium on VLSI Arne Heittmann, Tobias G. Noll
2012	—	`conf`	A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars. NANOARCH Arne Heittmann, Tobias G. Noll
2012	B	`conf`	A hybrid CMOS/memristive nanoelectronic circuit for programming synaptic weights. ESANN Arne Heittmann, Tobias G. Noll
2012	—	`conf`	A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations. ICSAMOS Matthias Korb, Tobias G. Noll
2012	—	`conf`	An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocks. SoCC Upasna Vishnoi, Michael Meixner, Tobias G. Noll
2012	—	`conf`	Efficient VLSI architectures of QPP interleavers for LTE turbo decoders. ISSoC Martin Broich, Tobias G. Noll
2012	—	`conf`	Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits. ACM Great Lakes Symposium on VLSI Arne Heittmann, Tobias G. Noll
2012	—	`conf`	Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme. SoCC Yuan Ren, Michael Gansen, Tobias G. Noll
2012	—	`conf`	Noise Margin Based Library Optimization Considering Variability in Sub-threshold. PATMOS Tobias Gemmeke, Maryam Ashouei, Tobias G. Noll
2011	—	`conf`	Area- and energy-efficient high-throughput LDPC decoders with low block latency. ESSCIRC Matthias Korb, Tobias G. Noll
2011	—	`conf`	Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization. ACM Great Lakes Symposium on VLSI Arne Heittmann, Tobias G. Noll
2011	J	`jnl`	Statistical modeling of reliability in logic devices. Microelectron. Reliab. Jochen Schleifer, Thomas Coenen, Tobias G. Noll
2010	—	`conf`	A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point. SoC Ingo Rust, Tobias G. Noll
2010	C	`conf`	A radix-4 single-precision floating point divider based on digit set interleaving. ISCAS Ingo Rust, Tobias G. Noll
2010	J	`jnl`	Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers. J. Signal Process. Syst. Götz Kappen, Lothor Kurz, O. Priebe, Tobias G. Noll
2010	—	`conf`	Interconnect routing of embedded FPGAs using standard VLSI routing tools. SoC Thomas Coenen, Jochen Schleifer, Oliver Weiß, Tobias G. Noll
2010	—	`conf`	LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates. SoC Matthias Korb, Tobias G. Noll
2010	J	`jnl`	MATLAB Meets LEGO Mindstorms - A Freshman Introduction Course Into Practical Engineering. IEEE Trans. Educ. Alexander Behrens, Linus Atorf, Robert Schwann, Bernd Neumann, Rainer Schnitzler, Johannes Ballé, Thomas Herold, Aulis Telle, Tobias G. Noll, Kay Hameyer, Til Aach
2010	—	`conf`	Potential of using block floating point arithmetic in ASIP-based GNSS-receivers. ASAP Emrah Tasdemir, Götz Kappen, Tobias G. Noll
2010	—	`ch.`	Reconfigurable Components for Application-Specific Processor Architectures. Dynamically Reconfigurable Systems Tobias G. Noll, Thorsten von Sydow, Bernd Neumann, Jochen Schleifer, Thomas Coenen, Götz Kappen
2009	—	`conf`	Area and latency optimized high-throughput Min-Sum based LDPC decoder architectures. ESSCIRC Matthias Korb, Tobias G. Noll
2008	J	`jnl`	A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. IEEE Trans. Very Large Scale Integr. Syst. Kieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias G. Noll
2008	—	`conf`	ASIP-eFPGA Architecture for Multioperable GNSS Receivers. SAMOS Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll
2008	B	`conf`	Adaptive kernel algorithm for FPGA-based speckle reduction. Image Processing Gerhard Tech, Robert Schwann, Götz Kappen, Michael Först, Tobias G. Noll
2008	J	`jnl`	Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs. J. Signal Process. Syst. Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll
2008	B	`conf`	Application-specific reconfigurable processors. FPL Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll
2008	A	`conf`	Design flow for embedded FPGAs based on a flexible architecture template. DATE Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll
2008	C	`conf`	Design of a Pareto-optimization environment and its application to motion estimation. MMSP Jörg von Livonius, Holger Blume, Tobias G. Noll
2008	J	`jnl`	OpenMP-based parallelization on an MPCore multiprocessor platform - A performance and power analysis. J. Syst. Archit. Holger Blume, Jörg von Livonius, Lisa Rotenberg, Tobias G. Noll, Harald Bothe, Jörg Brakensiek
2007	B	`conf`	A Power Estimation Model for an FPGA-based Softcore Processor. FPL Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll
2007	J	`jnl`	Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures. J. Syst. Archit. Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll
2007	—	`conf`	Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers. ASAP Götz Kappen, S. el Bahri, O. Priebe, Tobias G. Noll
2007	—	`conf`	Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory. ESSCIRC Alexander Flocke, Tobias G. Noll
2007	J	`jnl`	Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures. J. Syst. Archit. Holger Blume, Daniel Becker, Lisa Rotenberg, Martin Botteck, Jörg Brakensiek, Tobias G. Noll
2007	—	`conf`	Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform. ICSAMOS Holger Blume, Jörg von Livonius, Lisa Rotenberg, Tobias G. Noll, Harald Bothe, Jörg Brakensiek
2007	—	`conf`	Programmable Architectures for Realtime Music Decompression. PARCO Martin Botteck, Holger Blume, Jörg von Livonius, Martin Neuenhahn, Tobias G. Noll
2006	J	`jnl`	A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication Domain. J. VLSI Signal Process. Holger Blume, Thorsten von Sydow, Tobias G. Noll
2006	—	`conf`	A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. SoCC Kieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias G. Noll
2006	—	`conf`	Application specific instruction processor based implementation of a GNSS receiver on an FPGA. DATE Designers' Forum Götz Kappen, Tobias G. Noll
2006	A	`conf`	Cross disciplinary aspects (4G wireless special day). DATE Tobias G. Noll, Uwe Lambrette
2006	—	`conf`	Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. AICT/ICIW Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John V. McCanny
2006	A	`conf`	Design and analysis of matching circuit architectures for a closest match lookup. IPDPS Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John V. McCanny
2006	—	`conf`	Hybrid Functional and Instruction Level Power Modeling for Embedded Processors. SAMOS Holger Blume, Daniel Becker, Martin Botteck, Jörg Brakensiek, Tobias G. Noll
2006	—	`conf`	Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros. ReConFig Thorsten von Sydow, Matthias Korb, Bernd Neumann, Holger Blume, Tobias G. Noll
2006	—	`conf`	Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic. ASAP Thorsten von Sydow, Bernd Neumann, Holger Blume, Tobias G. Noll
2005	—	`conf`	A parametrizable low-power high-throughput turbo-decoder. ICASSP (5) Gordian Prescher, Tobias Gemmeke, Tobias G. Noll
2005	—	`conf`	Error-tolerant FIR filters based on low-cost residue codes. ISCAS (5) José L. Rodríguez-Navarro, Michael Gansen, Tobias G. Noll
2005	J	`jnl`	Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. J. VLSI Signal Process. Holger Blume, H. T. Feldkämper, Tobias G. Noll
2005	—	`conf`	Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets. SAMOS Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll
2004	—	`conf`	A Physically Oriented Model to Quantify the Noise-on-Delay Effect. PATMOS Tobias Gemmeke, Tobias G. Noll
2004	—	`conf`	A physically oriented model to quantify the dynamic noise margin [on-chip noise]. ESSCIRC Tobias Gemmeke, Tobias G. Noll
2004	J	`jnl`	Design optimization of low-power high-performance DSP building blocks. IEEE J. Solid State Circuits Tobias Gemmeke, Michael Gansen, Heinrich J. Stockmanns, Tobias G. Noll
2004	—	`conf`	Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets. SAMOS Holger Blume, Thorsten von Sydow, Tobias G. Noll
2004	C	`conf`	Segmentation in the loop: an iterative object-based algorithm for motion estimation. VCIP Holger Blume, Jörg von Livonius, Tobias G. Noll
2002	J	`jnl`	Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality. J. VLSI Signal Process. Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh, Tobias G. Noll
2002	J	`jnl`	Implementation of scalable power and area efficient high-throughput Viterbi decoders. IEEE J. Solid State Circuits Tobias Gemmeke, Michael Gansen, Tobias G. Noll
2002	—	`conf`	Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. ASAP Holger Blume, H. Hübert, H. T. Feldkämper, Tobias G. Noll
2002	J	`jnl`	Object based refinement of motion vector fields applying probabilistic homogenization rules. IEEE Trans. Consumer Electron. Holger Blume, G. Herczeg, O. Erdler, Tobias G. Noll
2000	—	`conf`	A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. ASAP V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, Jonathan J. Ashley, Razmik Karabed
2000	A	`conf`	A Hardware Implementation for Approximate Text Search in Multimedia Applications. IEEE International Conference on Multimedia and Expo (III) Hans-Martin Blüthgen, Patrick Osterloh, Holger Blume, Tobias G. Noll
2000	—	`conf`	A Programmable Processor for Approximate String Matching with High Throughput Rate. ASAP Hans-Martin Blüthgen, Tobias G. Noll
1998	J	`jnl`	A Flexible 200 GOPS HDTV Motion Estimation Chip. J. VLSI Signal Process. Jan Peter Berns, Tobias G. Noll
1998	Misc	`conf`	A hybrid equalizer merging the advantages of Baud spaced and fractionally spaced equalizers. ICASSP Christian Lütkemeyer, Hans-Martin Blüthgen, Tobias G. Noll
1998	—	`conf`	A new scalable VLSI architecture for Reed-Solomon decoders. CICC Wolfgang Wilhelm, A. Kaufmann, Tobias G. Noll
1998	J	`jnl`	A transversal equalizer with an increased adaptation speed and tracking capability. IEEE J. Solid State Circuits Christian Lütkemeyer, Tobias G. Noll
1998	—	`conf`	Architecture and implementation of a bitserial sorter for weighted median filtering. CICC Christiane Henning, Tobias G. Noll
1998	J	`jnl`	Device visualization for interventional MRI using local magnetic fields: Basic theory and its application to catheter visualization. IEEE Trans. Medical Imaging Arndt Glowinski, Jürgen Küsch, Gerhard Adam, Arno Bücker, Tobias G. Noll, Rolf W. Günther
1998	—	`conf`	Tiefenangepaßte Filterung für das Puls-Echo-Verfahren in der Ultraschalldiagnostik. Bildverarbeitung für die Medizin Robert Schwann, K. Eck, Andreas R. Brenner, Tobias G. Noll
1998	—	`conf`	Verbesserung der Dynamik und Ortsauflösung in der Ultraschalldiagnostik durch die Kombination kodierter Anregung und tiefenangepaßter Mismatched-Filterung. Bildverarbeitung für die Medizin K. Eck, Andreas R. Brenner, Wolfgang Wilhelm, Tobias G. Noll
1997	—	`conf`	A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays. ASAP Michael Gansen, Frank Richter, Oliver Weiss, Tobias G. Noll
1997	Misc	`conf`	A novel systematic mapping approach for highly efficient multiplexed FIR-filter architectures. ICASSP Wolfgang Wilhelm, Tobias G. Noll
1996	—	`conf`	A Flexible Motion Estimation Chip for Variable Size Block Matching. ASAP Jan Peter Berns, Tobias G. Noll
1996	—	`conf`	Artefaktreduzierung in der ultraschnellen Magnetresonanz-Bildgebung mittels inverser Filterung im Ortsfrequenzbereich. Bildverarbeitung für die Medizin S. Kannengießer, Andreas R. Brenner, Tobias G. Noll
1996	—	`conf`	Korrektur der Phasenaberration in Ultraschallaufnahmen durch das Dynamic-Time-Warping Verfahren. Bildverarbeitung für die Medizin K. Eck, Andreas R. Brenner, Tobias G. Noll
1995	J	`jnl`	Architecture and circuit design of a 6-GOPS signal processor for QAM demodulator applications. IEEE J. Solid State Circuits Erik De Man, Michael Schulz, Richard Schmidmaier, Matthias Schöbinger, Tobias G. Noll
1994	C	`conf`	A 60-MBaud Single-Chip QAM-Processor for the Complete Base-Band Signal Processing of QAM Demodulators. ISCAS Erik De Man, Matthias Schöbinger, Tobias G. Noll, Georg Sebald
1994	A*	`conf`	Low Power CMOS Design Strategies. DAC Matthias Schöbinger, Tobias G. Noll
1991	J	`jnl`	Carry-save architectures for high-speed digital signal processing. J. VLSI Signal Process. Tobias G. Noll
1990	Misc	`conf`	CMOS VLSI implementation of the 2D-DCT with linear processor arrays. ICASSP U. Totzek, F. Matthiesen, S. Wohlleben, Tobias G. Noll
1989	Misc	`conf`	VLSI architectures for the full-search blockmatching algorithm. ICASSP Luc de Vos, M. Stegherr, Tobias G. Noll
1984	Misc	`conf`	A dynamic time warp IC for a one thousand word recognition system. ICASSP Robert Kavaler, Robert W. Brodersen, Tobias G. Noll, Menahem Lowy, Hy Murveit
1984	Misc	`conf`	MOS-VLSI pipelined digital filters for video applications. ICASSP Walter Ulbrich, Tobias G. Noll, B. Zehner