Tingyuan Liang

26 papers A* 3A 8B 2Journal 12Unranked 1

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	DAPO: Design Structure-Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning. CoRR Jinming Ge, Linfeng Du, Likith Anaparty, Shangkun Li, Tingyuan Liang, Afzal Ahmad, Vivek Chaturvedi, Sharad Sinha, Zhiyao Xie, Jiang Xu, Wei Zhang
2024	A	`conf`	A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration. DATE Ya Wang, Hanwei Fan, Sicheng Li, Tingyuan Liang, Wei Zhang
2024	J	`jnl`	AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
2024	J	`jnl`	Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jian Peng, Tingyuan Liang, Jingbo Jiang, Yipu Zhang, Zhe Lin, Zhiyao Xie, Wei Zhang
2024	A*	`conf`	Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration. DAC Hanwei Fan, Ya Wang, Sicheng Li, Tingyuan Liang, Wei Zhang
2024	J	`jnl`	Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration. CoRR Hanwei Fan, Ya Wang, Sicheng Li, Tingyuan Liang, Wei Zhang
2024	J	`jnl`	FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs. ACM Trans. Reconfigurable Technol. Syst. Linfeng Du, Tingyuan Liang, Xiaofeng Zhou, Jinming Ge, Shangkun Li, Sharad Sinha, Jieru Zhao, Zhiyao Xie, Wei Zhang
2024	A	`conf`	GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. FPGA Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang
2023	—	`conf`	DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis. ICFPT Liangji Chen, Tingyuan Liang, Wei Zhang, Sharad Sinha
2023	A	`conf`	FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. FPGA Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
2023	J	`jnl`	HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang
2023	A	`conf`	MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor Network. ICCAD Weihua Xiao, Shanshan Han, Yue Yang, Shaoze Yang, Cheng Zheng, Jingsong Chen, Tingyuan Liang, Lei Li, Weikang Qian
2023	A*	`conf`	PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN. DAC Jian Peng, Tingyuan Liang, Zhiyao Xie, Wei Zhang
2022	J	`jnl`	AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA. CoRR Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
2022	J	`jnl`	AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining. CoRR Tingyuan Liang, Jingsong Chen, Lei Li, Wei Zhang
2022	J	`jnl`	FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. CoRR Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
2021	A	`conf`	AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. ICCAD Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
2020	B	`conf`	FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. FPL Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
2020	J	`jnl`	FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. CoRR Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
2019	A	`conf`	A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. FPGA Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019	A	`conf`	Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. ICCAD Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
2019	A*	`conf`	LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. DAC Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019	A	`conf`	Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. DATE Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019	J	`jnl`	Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. CoRR Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2018	J	`jnl`	Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
2017	B	`conf`	PAAS: A system level simulator for heterogeneous computing architectures. FPL Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang