TingTing Hwang

112 papers A* 7A 26B 2C 3Misc 1Journal 48Unranked 25
YearRankTypeTitle / Venue / Authors
2025 J jnl
Expanding and Obfuscating In-Cone Trees to Resist SAT Attack in Logic Locking.
IEEE Trans. Reliab.
Ruijie Wang, Li-Nung Hsu, Yung-Chih Chen, TingTing Hwang
2025 A conf
Using OFF-set only for Corrupting Circuit to Resist Structural Attack in CAC Locking.
DATE
Hsiang-Chun Cheng, Ruijie Wang, TingTing Hwang
2024 J jnl
A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration.
ACM Trans. Design Autom. Electr. Syst.
Cheng-Hsien Lin, Kuan-Ting Chen, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
2024 A conf
A Hybrid Approach to Reverse Engineering on Combinational Circuits.
DATE
Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang
2023 A conf
Expanding In-Cone Obfuscated Tree for Anti SAT Attack.
DATE
Ruijie Wang, Li-Nung Hsu, Yung-Chih Chen, TingTing Hwang
2023 — conf
M-Party: A Secure Dynamic Cache Partitioning by More Than Two Parties.
SOCC
Yuan-Tai Lin, Chin-Yu Sun, TingTing Hwang
2021 — conf
A Dynamic Link-latency Aware Cache Replacement Policy (DLRP).
ASP-DAC
Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang
2021 J jnl
A New Attack for Self-Certified Digital Signatures for E-commerce Applications.
J. Inf. Sci. Eng.
Chin-Yu Sun, Hsiao-Ling Wu, Hung-Min Sun, TingTing Hwang
2021 J jnl
A novel privacy-preserving deep learning scheme without a cryptography component.
Comput. Electr. Eng.
Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang
2019 J jnl
A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component.
CoRR
Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang
2019 — conf
Crosstalk-aware TSV-buffer Insertion in 3D IC.
SoCC
Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, TingTing Hwang
2019 — conf
Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs.
SoCC
Pei-An Ho, Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang
2017 J jnl
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
2017 A conf
Architectural evaluations on TSV redundancy for reliability enhancement.
DATE
Yen-Hao Chen, Chien-Pang Chiu, Russell Barnes, TingTing Hwang
2017 — conf
Communication driven remapping of processing element (PE) in fault-tolerant NoC-based MPSoCs.
ASP-DAC
Chia-Ling Chen, Yen-Hao Chen, TingTing Hwang
2016 A conf
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements.
DATE
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
2016 J jnl
Architecture of Ring-Based Redundant TSV for Clustered Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Wei-Hen Lo, Kang Chi, TingTing Hwang
2016 A conf
Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC).
DATE
Wei-Hen Lo, Kai-zen Liang, TingTing Hwang
2015 A conf
Architecture of ring-based redundant TSV for clustered faults.
DATE
Wei-Hen Lo, Kang Chi, TingTing Hwang
2014 J jnl
Clock-Tree Synthesis with Methodology of Reuse in 3D-IC.
ACM J. Emerg. Technol. Comput. Syst.
Fu-Wei Chen, TingTing Hwang
2014 A conf
Compaction-free compressed cache for high performance multi-core system.
ICCAD
Po-Yang Hsu, Pei-Lan Lin, TingTing Hwang
2014 — conf
Fault-tolerant TSV by using scan-chain test TSV.
ASP-DAC
Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang
2014 J jnl
Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang
2014 J jnl
Utilizing Circuit Structure for Scan Chain Diagnosis.
IEEE Trans. Very Large Scale Integr. Syst.
Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang
2013 — conf
Stacking signal TSV for thermal dissipation in global routing for 3D IC.
ASP-DAC
Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang
2013 J jnl
Thermal-aware memory mapping in 3D designs.
ACM Trans. Embed. Comput. Syst.
Ang-Chih Hsieh, TingTing Hwang
2013 A conf
Thread-criticality aware dynamic cache reconfiguration in multi-core system.
ICCAD
Po-Yang Hsu, TingTing Hwang
2013 B conf
Utilizing circuit structure for scan chain diagnosis.
ETS
Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang
2012 J jnl
A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction.
IEEE Trans. Very Large Scale Integr. Syst.
Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang
2012 A* conf
Clock tree synthesis with methodology of re-use in 3D IC.
DAC
Fu-Wei Chen, TingTing Hwang
2012 J jnl
Run-Time Reconfiguration of Expandable Cache for Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Ang-Chih Hsieh, TingTing Hwang
2012 J jnl
TSV Redundancy: Architecture and Design Issues in 3-D IC.
IEEE Trans. Very Large Scale Integr. Syst.
Ang-Chih Hsieh, TingTing Hwang
2011 A conf
A new architecture for power network in 3D IC.
DATE
Hsien-Te Chen, Hong-Long Lin, Zicheng Wang, TingTing Hwang
2011 — conf
A physical-location-aware fault redistribution for maximum IR-drop reduction.
ASP-DAC
Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang
2011 — conf
Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation.
ASP-DAC
Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang
2011 B conf
Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms.
ICPP
Ang-Chih Hsieh, Yi-Ta Wu, Shau-Yin Tseng, TingTing Hwang
2010 J jnl
A Fast Digital Chaotic Generator for Secure Communication.
Int. J. Bifurc. Chaos
Shih-Liang Chen, TingTing Hwang, Shu-Ming Chang, Wen-Wei Lin
2010 J jnl
A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wen-Wen Hsieh, Shih-Liang Chen, I-Sheng Lin, TingTing Hwang
2010 J jnl
Randomness Enhancement Using Digitalized Modified Logistic Map.
IEEE Trans. Circuits Syst. II Express Briefs
Shih-Liang Chen, TingTing Hwang, Wen-Wei Lin
2010 J jnl
Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization.
IEEE Trans. Very Large Scale Integr. Syst.
Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang
2010 A conf
TSV redundancy: Architecture and design issues in 3D IC.
DATE
Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li
2009 A conf
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test.
DATE
Wen-Wen Hsieh, I-Sheng Lin, TingTing Hwang
2009 J jnl
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques.
ACM Trans. Design Autom. Electr. Syst.
Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma
2009 A* conf
New spare cell design for IR drop minimization in Engineering Change Order.
DAC
Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang
2009 J jnl
Skew-aware polarity assignment in clock tree.
ACM Trans. Design Autom. Electr. Syst.
Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang
2009 A conf
Thermal-aware memory mapping in 3D designs.
DATE
Ang-Chih Hsieh, TingTing Hwang
2009 — conf
Thermal-aware post compilation for VLIW architectures.
ASP-DAC
Wen-Wen Hsieh, TingTing Hwang
2008 J jnl
Digital Secure-Communication Using Robust Hyper-Chaotic Systems.
Int. J. Bifurc. Chaos
Shih-Liang Chen, Shu-Ming Chang, Wen-Wei Lin, TingTing Hwang
2008 J jnl
Synthesis of a novel timing-error detection architecture.
ACM Trans. Design Autom. Electr. Syst.
Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang
2008 A conf
Transition-aware decoupling-capacitor allocation in power noise reduction.
ICCAD
Po-Yuan Chen, Che-Yu Liu, TingTing Hwang
2007 J jnl
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang
2007 J jnl
A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.
ACM Trans. Design Autom. Electr. Syst.
Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang
2007 J jnl
Crosstalk-Aware Domino-Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Yu Liu, TingTing Hwang
2007 J jnl
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains.
J. Supercomput.
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang
2007 J jnl
Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu
2007 A conf
Skew aware polarity assignment in clock tree.
ICCAD
Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang
2006 Misc conf
A bus architecture for crosstalk elimination in high performance processor design.
CODES+ISSS
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
2006 J jnl
A power-driven multiplication instruction-set design method for ASIPs.
IEEE Trans. Very Large Scale Integr. Syst.
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
2006 J jnl
Crosstalk minimization in logic synthesis for PLAs.
ACM Trans. Design Autom. Electr. Syst.
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
2006 A conf
Crosstalk-aware domino logic synthesis.
DATE
Yi-Yu Liu, TingTing Hwang
2006 J jnl
Decomposition of instruction decoders for low-power designs.
ACM Trans. Design Autom. Electr. Syst.
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
2006 J jnl
Instruction buffering for nested loops in low-power design.
IEEE Trans. Very Large Scale Integr. Syst.
Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang
2006 C conf
Performance-driven crosstalk elimination at post-compiler level.
ISCAS
Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu
2006 — conf
Switching-activity driven gate sizing and Vth assignment for low power design.
ASP-DAC
Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
2005 — conf
A power-driven multiplication instruction-set design method for ASIPs.
ISCAS (4)
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
2005 — conf
Functionality directed clustering for low power MTCMOS design.
ASP-DAC
Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu
2005 — conf
Low-power techniques for network security processors.
ASP-DAC
Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu
2004 A conf
Crosstalk Minimization in Logic Synthesis for PLA.
DATE
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
2004 A conf
Decomposition of Instruction Decoder for Low Power Design.
DATE
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
2004 — conf
Low power design using dual threshold voltage.
ASP-DAC
Yen-Te Ho, TingTing Hwang
2004 — conf
Output-pattern directed decomposition for low power design.
ISCAS (5)
Chi-Wei Hu, TingTing Hwang
2004 — conf
Power-Aware Scheduling for Parallel Security Processors with Analytical Models.
LCPC
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang
2003 A conf
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs.
DATE
Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
2003 J jnl
Compiler optimization on VLIW instruction scheduling for low power.
ACM Trans. Design Autom. Electr. Syst.
Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai
2003 A conf
Decomposition of Extended Finite State Machine for Low Power Design.
DATE
MingHung Lee, TingTing Hwang, Shi-Yu Huang
2003 A conf
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer.
DATE
Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
2002 — conf
A technology mapping algorithm for CPLD architectures.
FPT
Shih-Liang Chen, TingTing Hwang, C. L. Liu
2002 — conf
Instruction buffering for nested loops in low power design.
ISCAS (4)
Chi Ta Wu, TingTing Hwang
2002 J jnl
Logic transformation for low-power synthesis.
ACM Trans. Design Autom. Electr. Syst.
Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
2001 — conf
A construction of minimal delay Steiner tree using two-pole delay model.
ASP-DAC
LiYi Lin, Yi-Yu Liu, TingTing Hwang
2001 J jnl
Architecture driven circuit partitioning.
IEEE Trans. Very Large Scale Integr. Syst.
Chau-Shen Chen, TingTing Hwang, C. L. Liu
2001 A conf
Binary decision diagram with minimum expected path length.
DATE
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu
2000 — conf
Compiler Optimization on Instruction Scheduling for Low Power.
ISSS
Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai
1999 — conf
A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning.
ASP-DAC
Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang
1999 A conf
Logic Transformation for Low Power Synthesis.
DATE
Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
1999 J jnl
On determining sensitization criterion in an iterative gate sizing process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
How-Rern Lin, TingTing Hwang
1998 A* conf
A Re-engineering Approach to Low Power FPGA Design Using SPFD.
DAC
Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang
1998 A conf
Architecture driven circuit partitioning.
ICCAD
Chau-Shen Chen, TingTing Hwang, C. L. Liu
1998 J jnl
Layout Driven Selection and Chaining of Partial Scan Flip-Flops.
J. Electron. Test.
Chau-Shen Chen, TingTing Hwang
1997 J jnl
Boolean matching for incompletely specified functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuo-Hua Wang, TingTing Hwang
1997 A* conf
Low Power FPGA Design - A Re-engineering Approach.
DAC
Chau-Shen Chen, TingTing Hwang, C. L. Liu
1997 J jnl
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang
1996 J jnl
Cell height driven transistor sizing in a cell based static CMOS module design.
IEEE J. Solid State Circuits
How-Rern Lin, Yu-Chin Hsu, TingTing Hwang
1996 J jnl
Exploiting communication complexity for Boolean matching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuo-Hua Wang, TingTing Hwang, Cheng Chen
1996 A* conf
Layout Driven Selecting and Chaining of Partial Scan.
DAC
Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang
1996 J jnl
Low power realization of finite state machines - a decomposition approach.
ACM Trans. Design Autom. Electr. Syst.
Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu
1996 J jnl
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang
1995 A* conf
Boolean Matching for Incompletely Specified Functions.
DAC
Kuo-Hua Wang, TingTing Hwang
1995 J jnl
Combining technology mapping and placement for delay-minimization in FPGA designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1995 — conf
Power recduction by gate sizing with path-oriented slack calculation.
ASP-DAC
How-Rern Lin, TingTing Hwang
1994 — conf
Cell Height Driven Transistor Sizing in a Cell Based Module Design.
EDAC-ETC-EUROASIC
How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang
1994 A conf
Dynamical identification of critical paths for iterative gate sizing.
ICCAD
How-Rern Lin, TingTing Hwang
1994 J jnl
Logic synthesis for field-programmable gate arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang
1994 J jnl
Performance-driven interconnection optimization for microarchitecture synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin
1994 C conf
State Assignment for Power and Area Minimization.
ICCD
Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1993 A conf
Combining technology mapping and placement for delay-optimization in FPGA designs.
ICCAD
Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1992 J jnl
ELM-A Fast Addition Algorithm Discovered by a Program.
IEEE Trans. Computers
Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang
1992 J jnl
Efficiently computing communication complexity for multilevel logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
1992 — conf
Performance-driven interconnection optimization for microarchitecture synthesis.
EURO-DAC
Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Yaun-Long Lin
1990 J jnl
Exploiting communication complexity for multilevel logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
1990 C conf
Logic synthesis for programmable logic devices.
ICCD
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
1989 A* conf
Multi-Level Logic Synthesis Using Communication Complexity.
DAC
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin