Ting Wu - RankMe

12 papers C 1Misc 1Journal 5Unranked 5

Year	Rank	Type	Title / Venue / Authors
2012	J	`jnl`	A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. IEEE J. Solid State Circuits Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan
2012	J	`jnl`	A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. IEEE J. Solid State Circuits Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan
2010	Misc	`conf`	Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link. VLSI Design Leneesh Raghavan, Ting Wu
2010	—	`conf`	Low-skew clock distribution using zero-phase-clock-buffer DLLs. ISSCC Ting Wu, Farshid Aryanfar, Haechang Lee, Jie Shen, T. J. Chin, Carl W. Werner, Ken Chang
2009	J	`jnl`	A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. IEEE J. Solid State Circuits Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi
2009	J	`jnl`	Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. IEEE J. Solid State Circuits Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2008	—	`conf`	Clocking circuits for a 16Gb/s memory interface. CICC Ting Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun, T. J. Chin, Jie Shen, Rich Perego, Ken Chang
2008	—	`conf`	Noise tolerant oscillator design using perturbation projection vector analysis. CICC Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2007	—	`conf`	A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. CICC Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2007	J	`jnl`	An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators. IEEE J. Solid State Circuits Ting Wu, Kartikeya Mayaram, Un-Ku Moon
2006	C	`conf`	Dependence of LC VCO oscillation frequency on bias current. ISCAS Ting Wu, Un-Ku Moon, Kartikeya Mayaram
2005	—	`conf`	An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. ISCAS (4) Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram