Ting-Ting Y. Lin

16 papers A* 3A 2Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
1997 J jnl
The Faulty Behavior of Feedforward Neural Networks with Hard-limiting Activation Fuction.
Neural Comput.
Zhiyu Tian, Ting-Ting Y. Lin, Shiyuan Yang, Shibai Tong
1996 A* conf
Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming.
DAC
Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng
1996 A* conf
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing.
DAC
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho
1996 J jnl
Optimal wire sizing and buffer insertion for low power and a generalized delay model.
IEEE J. Solid State Circuits
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
1996 — conf
Simultaneous Routing and Buffer Insertion for High Performance Interconnect.
Great Lakes Symposium on VLSI
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995 J jnl
Circuit clustering using a stochastic flow injection method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995 A conf
Optimal wire sizing and buffer insertion for low power and a generalized delay model.
ICCAD
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995 J jnl
Optimization by iterative improvement: an experimental evaluation on two-way partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995 — conf
Optimization of power dissipation and skew sensitivity in clock buffer synthesis.
ISLPD
Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995 — conf
Performance driven multiple-source bus synthesis using buffer insertion.
ASP-DAC
Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
1994 J jnl
A general purpose, multiple-way partitioning algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
1994 — conf
Performability analysis of non-repairable multicomponent systems using order statistics.
SPDP
Amiya Bhattacharya, Ramesh R. Rao, Ting-Ting Y. Lin
1993 J jnl
A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy.
IEEE Des. Test Comput.
Ting-Ting Y. Lin, Huoy-Yu Liou
1993 — conf
Delay Analysis in Synchronous Circuit-Switched Delta Networks.
IPPS
Amiya Bhattacharya, Ramesh R. Rao, Ting-Ting Y. Lin
1992 A conf
A probabilistic multicommodity-flow solution to circuit clustering problems.
ICCAD
Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
1991 A* conf
A General Purpose Multiple Way Partitioning Algorithm.
DAC
Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin