Ting-Chi Wang - RankMe

119 papers A* 6A 20B 2C 6Journal 28Unranked 55

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	An Effective Placement Framework for Designs with Half-Row-Extended Cells. ASP-DAC Po-Yi Wu, Tzu-Sheng Hung, Wai-Kei Mak, Ting-Chi Wang
2026	—	`conf`	An Improved Ion-Shuttling Approach for QCCD Architectures. ISPD Tung-Yeh Wu, Ting-Chi Wang
2026	J	`jnl`	GenPart 2.0: Enhanced Hypergraph Partitioning with Vertex Weight Handling using a Generative Model. ACM Trans. Design Autom. Electr. Syst. Magi Chen, Ting-Chi Wang
2026	J	`jnl`	Parallel Delay-Driven Layer Assignment Leveraging Hierarchical Task Graph Modeling for Advanced Technology Nodes. IEEE Trans. Computers Zepeng Li, Zhen Zhuang, Genggeng Liu, Wen-Hao Liu, Tsung-Yi Ho, Ting-Chi Wang
2025	—	`conf`	A Machine Learning-Assisted Placement Flow with Pin Accessibility Awareness. ACM Great Lakes Symposium on VLSI Min-Feng Hsieh, Ting-Chi Wang
2025	—	`conf`	A PPA- and Security-Aware Physical Design Flow. ISQED Chun-Wei Chiu, Ting-Chi Wang
2025	J	`jnl`	A Unified Deep Reinforcement Learning Approach for Constructing Rectilinear and Octilinear Steiner Minimum Tree. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhenkun Lin, Genggeng Liu, Xing Huang, Yibo Lin, Jixin Zhang, Wen-Hao Liu, Ting-Chi Wang
2025	—	`conf`	An Effective and Efficient Qubit Mapping Approach for Trapped-Ion Quantum Computers. ACM Great Lakes Symposium on VLSI Liang-Yu Lai, Ting-Chi Wang
2025	C	`conf`	Analyzing and Enhancing the Reliability of Vision Transformer Models Against Soft Errors. ISCAS En-Yu Liao, Ting-Chi Wang
2025	A*	`conf`	GPart: A GNN-Enabled Multilevel Graph Partitioner. DAC Magi Chen, Ting-Chi Wang
2025	J	`jnl`	HyperPlace: Harnessing a Large Language Model for Efficient Hyperparameter Optimization in GPU-Accelerated VLSI Placement. ACM Trans. Design Autom. Electr. Syst. Magi Chen, Ting-Chi Wang
2025	A	`conf`	Leveraging GPU for Better Detailed Placement Quality. ICCAD Chen-Han Lu, Wen-Hao Liu, Haoxing Ren, Ting-Chi Wang
2025	J	`jnl`	SPTA 2.0: Enhanced Scalable Parallel Track Assignment Algorithm with Two-Stage Partition Considering Timing Delay. ACM Trans. Design Autom. Electr. Syst. Huayang Cai, Pengcheng Huang, Genggeng Liu, Xing Huang, Yidan Jing, Wenhao Liu, Ting-Chi Wang
2025	J	`jnl`	Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Trans. Cryptogr. Hardw. Embed. Syst. Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini
2024	—	`conf`	A Bounding Box-based Net Partitioning Method for Double-sided Routing. ACM Great Lakes Symposium on VLSI Fang-Yu Hsu, Tzu-Chuan Lin, Wai-Kei Mak, Ting-Chi Wang
2024	B	`conf`	A Fast and Robust Global Router with Capacity Reduction Techniques. ASPDAC Yun-Kai Fang, Ye-Chih Lin, Ting-Chi Wang
2024	A	`conf`	A Hybrid Approach to Reverse Engineering on Combinational Circuits. DATE Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang
2024	A	`conf`	A Hypergraph Partitioner Utilizing a Novel Graph Generative Model. ICCAD Magi Chen, Ting-Chi Wang
2024	A	`conf`	An Effective ECO Methodology for Reducing Back-side Design Rule Violations in Double-sided Signal Routing. ICCAD Che-Ping Tsai, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang
2024	B	`conf`	An Effective Netlist Planning Approach for Double-sided Signal Routing. ASPDAC Tzu-Chuan Lin, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang
2024	—	`conf`	Pioneering Contributions of Professor Martin D. F. Wong to Automatic Floorplan Design. ISPD Ting-Chi Wang
2024	—	`conf`	SMT-Based Layout Synthesis Approaches for Quantum Circuits. ISPD Zi-Hao Guo, Ting-Chi Wang
2024	J	`jnl`	Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Cryptol. ePrint Arch. Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini
2023	—	`conf`	A Macro Legalization Approach Considering Minimum Channel Spacing and Buffer Area Reservation Constraints. ACM Great Lakes Symposium on VLSI Chun-Wei Chiu, Yun-Kai Fang, Shao-Ting Chung, Ting-Chi Wang
2023	—	`conf`	A Robust Routing Guide Generation Approach for Mixed-Size Designs. MLCAD Zhi-Hong Lee, Chen-Han Lu, Hsin-Hung Pan, Ting-Chi Wang, Po-Yuan Chen, Cindy Chin-Fang Shen
2023	C	`conf`	Fast and Accurate Detection of Audio Adversarial Examples. ISCAS Po-Hao Huang, Yung-Yuan Lan, Wilbert Harriman, Venesia Chiuwanara, Ting-Chi Wang
2023	—	`conf`	Hybrid-Row-Height Design Placement Legalization Considering Cell Variants. ACM Great Lakes Symposium on VLSI Syuan-Han Liang, Tsu-Ling Hsiung, Wai-Kei Mak, Ting-Chi Wang
2023	—	`conf`	Routability-aware Placement Guidance Generation for Mixed-size Designs. ISQED Chieh-Yu Cheng, Ting-Chi Wang
2022	J	`jnl`	Generation of Black-box Audio Adversarial Examples Based on Gradient Approximation and Autoencoders. ACM J. Emerg. Technol. Comput. Syst. Po-Hao Huang, Honggang Yu, Max Panoff, Ting-Chi Wang
2022	A	`conf`	Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. ICCAD Meng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, Ting-Chi Wang
2022	—	`conf`	HybridGP: Global Placement for Hybrid-Row-Height Designs. ASP-DAC Kuan-Yu Chen, Hsiu-Chu Hsu, Wai-Kei Mak, Ting-Chi Wang
2022	C	`conf`	LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction. VLSI-SoC Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang
2022	—	`conf`	On Predicting Solution Quality of Maze Routing Using Convolutional Neural Network. ISQED Kuei-Huan Chang, Hsin-Hung Pan, Ting-Chi Wang, Po-Yuan Chen, Cindy Chin-Fang Shen
2022	C	`conf`	SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition. VLSI-SoC Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang
2022	J	`jnl`	Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Genggeng Liu, Xinghai Zhang, Wenzhong Guo, Xing Huang, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang
2021	—	`conf`	Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs. ISPD Bo-Yang Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang
2020	A	`conf`	An Algorithm for Rule-based Layout Pattern Matching. ICCAD Sheng-Hao Wang, Yen-Jong Chen, Ting-Chi Wang, Oscar Chen
2020	—	`conf`	Audio Adversarial Examples Generation with Recurrent Neural Networks ASP-DAC Kuei-Huan Chang, Po-Hao Huang, Honggang Yu, Yier Jin, Ting-Chi Wang
2020	—	`conf`	Forensic Artifacts of Network Traffic on WeChat Calls. ICACT Da-Yu Kao, Ting-Chi Wang, Fu-Ching Tsai
2020	A	`conf`	MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes. DATE Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang
2020	—	`conf`	MiniDeviation: An Efficient Multi-Stage Bus-Aware Global Router. VLSI-DAT Weida Zhu, Xinghai Zhang, Genggeng Liu, Wenzhong Guo, Ting-Chi Wang
2019	A	`conf`	A Mixed-Height Standard Cell Placement Flow for Digital Circuit Blocks DATE Yi-Cheng Zhao, Yu-Chieh Lin, Ting-Chi Wang, Ting-Hsiung Wang, Yun-Ru Wu, Hsin-Chang Lin, Shu-Yi Kao
2019	—	`conf`	RDTA: An Efficient Routability-Driven Track Assignment Algorithm. ACM Great Lakes Symposium on VLSI Genggeng Liu, Zhen Zhuang, Wenzhong Guo, Ting-Chi Wang
2018	A	`conf`	A practical detailed placement algorithm under multi-cell spacing constraints. ICCAD Yu-Hsiang Cheng, Ding-wei Huang, Wai-Kei Mak, Ting-Chi Wang
2018	—	`conf`	Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. ISVLSI Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang
2017	J	`jnl`	A routing framework for technology migration with bump encroachment. Integr. Po-Yi Wu, Wai-Kei Mak, Ting-Chi Wang, Cheng Zhuo, Kassan Unda, Yiyu Shi
2017	—	`conf`	Delay-driven layer assignment for advanced technology nodes. ASP-DAC Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang
2017	A	`conf`	On refining standard cell placement for self-aligned double patterning. DATE Ye-Hong Chen, Sheng-He Wang, Ting-Chi Wang
2016	—	`conf`	Negotiation-based track assignment considering local nets. ASP-DAC Man-Pan Wong, Wen-Hao Liu, Ting-Chi Wang
2016	A	`conf`	Online slack-time binning for IO-registered die-to-die interconnects. ITC Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng
2015	—	`conf`	A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography. ISPD Hsi-An Chien, Szu-Yuan Han, Ye-Hong Chen, Ting-Chi Wang
2015	J	`jnl`	On Refining Row-Based Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsi-An Chien, Ye-Hong Chen, Szu-Yuan Han, Hsiu-Yu Lai, Ting-Chi Wang
2015	J	`jnl`	Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang
2014	A	`conf`	A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy. ICCAD Wen-Hao Liu, Zhen-Yu Peng, Ting-Chi Wang
2014	—	`conf`	A study on the use of parallel wiring techniques for sub-20nm designs. ACM Great Lakes Symposium on VLSI Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh
2014	—	`conf`	A study on unroutable placement recognition. ISPD Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang
2014	A*	`conf`	Density-aware Detailed Placement with Instant Legalization. DAC Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang
2014	J	`jnl`	Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Hung Liu, Chun-Xun Lin, I-Che Chen, D. T. Lee, Ting-Chi Wang
2014	A*	`conf`	Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs. DAC Wen-Hao Liu, Min-Sheng Chang, Ting-Chi Wang
2014	A	`conf`	Mask-cost-aware ECO routing DATE Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang
2014	A	`conf`	Metal layer planning for silicon interposers with consideration of routability and manufacturing cost. DATE Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang
2014	—	`conf`	Redundant-via-aware ECO routing. ASP-DAC Hsi-An Chien, Ting-Chi Wang
2013	—	`conf`	An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. ASP-DAC Bo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang
2013	J	`jnl`	Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. IEEE Trans. Very Large Scale Integr. Syst. Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang
2012	J	`jnl`	Pad Assignment for Die-Stacking System-in-Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang
2011	—	`conf`	An enhanced global router with consideration of general layer directives. ISPD Tsung-Hsien Lee, Yen-Jung Chang, Ting-Chi Wang
2011	—	`conf`	Simultaneous redundant via insertion and line end extension for yield optimization. ASP-DAC Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
2011	J	`jnl`	Through-Silicon Via Planning in 3-D Floorplanning. IEEE Trans. Very Large Scale Integr. Syst. Ming-Chao Tsai, Ting-Chi Wang, Ting Ting Hwang
2010	J	`jnl`	Enhanced Double Via Insertion Using Wire Bending. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang
2010	A	`conf`	GLADE: A modern global router considering layer directives. ICCAD Yen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang
2010	J	`jnl`	NTHU-Route 2.0: A Robust Global Router for Modern Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yen-Jung Chang, Yu-Ting Lee, Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang
2010	J	`jnl`	Optimal Double Via Insertion With On-Track Preference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
2010	A	`conf`	Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing. ICCAD Tsung-Hsien Lee, Ting-Chi Wang
2010	—	`conf`	Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. ACM Great Lakes Symposium on VLSI De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang
2009	A	`conf`	Pad assignment for die-stacking System-in-Package design. ICCAD Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang
2009	—	`conf`	Redundant via insertion with wire bending. ISPD Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang
2009	—	`conf`	Robust layer assignment for via optimization in multi-layer global routing. ISPD Tsung-Hsien Lee, Ting-Chi Wang
2008	A*	`conf`	A generalized network flow based algorithm for power-aware FPGA memory mapping. DAC Tien-Yuan Hsu, Ting-Chi Wang
2008	—	`conf`	A new global router for modern designs. ASP-DAC Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang
2008	—	`conf`	An MILP-based wire spreading algorithm for PSM-aware layout modification. ASP-DAC Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang
2008	J	`jnl`	Congestion-Constrained Layer Assignment for Via Minimization in Global Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsung-Hsien Lee, Ting-Chi Wang
2008	J	`jnl`	Fast and Optimal Redundant Via Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao
2008	A	`conf`	NTHU-Route 2.0: a fast and stable global router. ICCAD Yen-Jung Chang, Yu-Ting Lee, Ting-Chi Wang
2008	—	`conf`	Optimal post-routing redundant via insertion. ISPD Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao
2008	—	`ch.`	Slicing Floorplans. Handbook of Algorithms for Physical Design Automation Ting-Chi Wang, Martin D. F. Wong
2007	—	`conf`	A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. ASP-DAC Pei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang
2007	—	`conf`	Fast Buffered Delay Estimation Considering Process Variations. ASP-DAC Tien-Ting Fang, Ting-Chi Wang
2007	—	`conf`	Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang
2006	A	`conf`	Post-routing redundant via insertion and line end extension with via density consideration. ICCAD Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
2006	—	`conf`	Post-routing redundant via insertion for yield/reliability improvement. ASP-DAC Kuang-Yao Lee, Ting-Chi Wang
2005	—	`conf`	Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. ASP-DAC Zhong-Ching Lu, Ting-Chi Wang
2005	—	`conf`	Maze routing with OPC consideration. ASP-DAC Yun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang
2005	—	`conf`	Simple yet effective algorithms for block and I/O buffer placement in flip-chip design. ISCAS (2) Hao-Yueh Hsieh, Ting-Chi Wang
2004	J	`jnl`	Multilevel circuit clustering for delay minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang
2003	J	`jnl`	Optimal circuit clustering for delay minimization under a more general delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cliff C. N. Sze, Ting-Chi Wang
2003	—	`conf`	Performance-driven multi-level clustering for combinational circuits. ASP-DAC Chin Ngai Sze, Ting-Chi Wang
2002	—	`conf`	Module placement with pre-placed modules using the corner block list representation. ISCAS (1) S. Dhamdhere, Ningyu Zhou, Ting-Chi Wang
2002	—	`conf`	Multi-Level Circuit Clustering for Delay Minimization. IWLS Cliff C. N. Sze, Ting-Chi Wang
2002	—	`conf`	Optimal circuit clustering with variable interconnect delay. ISCAS (4) Cliff C. N. Sze, Ting-Chi Wang
2001	—	`conf`	Module placement with boundary constraints using the sequence-pair representation. ASP-DAC Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang
2001	—	`conf`	Module placement with pre-placed modules using the B*-tree representation. ISCAS (5) Yi-He Jiang, Jianbang Lai, Ting-Chi Wang
2001	—	`conf`	Power minization in LUT-based FPGA technology mapping. ASP-DAC Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang
2001	—	`conf`	Slicing floorplan design with boundary-constrained modules. ISPD En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang
2000	—	`conf`	Feasible two-way circuit partitioning with complex resource constraints. ASP-DAC Hsun-Cheng Lee, Ting-Chi Wang
2000	C	`conf`	On accelerating slicing floorplan design with boundary constraints. ISCAS En-Cheng Liu, Tu-Hsing Lin, Ting-Chi Wang
2000	—	`conf`	On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer
1999	—	`conf`	Faster and Better Spectral Algorithms for Multi-Way Partitioning. ASP-DAC Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang
1997	J	`jnl`	Routing for symmetric FPGAs and FPICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
1995	J	`jnl`	Optimal net assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong
1995	J	`jnl`	Performance-driven channel pin assignment algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. T. W. Her, Ting-Chi Wang, Martin D. F. Wong
1993	C	`conf`	A Graph Partitioning Problem for Multiple-chip Design. ISCAS Yao-Ping Chen, Ting-Chi Wang, D. F. Wong
1993	—	`ch.`	A note on the Complexity of Stockmeyer's floorplan Optimization Technique. Algorithmic Aspects of VLSI Layout Ting-Chi Wang, D. F. Wong
1993	J	`jnl`	Graph-based techniques to speed up floorplan area optimization. Integr. Ting-Chi Wang, D. F. Wong
1993	—	`conf`	On over-the-cell channel routing. EURO-DAC Ting-Chi Wang, D. F. Wong, Yachyang Sun, C. K. Wong
1993	A	`conf`	Routing for symmetric FPGAs and FPICs. ICCAD Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
1992	A*	`conf`	A Graph Theoretic Technique to Speed up Floorplan Area Optimization. DAC Ting-Chi Wang, D. F. Wong
1992	J	`jnl`	Optimal floorplan area optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ting-Chi Wang, Martin D. F. Wong
1991	—	`conf`	Efficient shape curve construction in floorplan design. EURO-DAC Ting-Chi Wang, D. F. Wong
1990	A*	`conf`	An Optimal Algorithm for Floorplan Area Optimization. DAC Ting-Chi Wang, D. F. Wong