Tim Kerins

20 papers A 1B 4Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2007 — conf
A Reconfigurable Processor for the Cryptographic nT Pairing in Characteristic 3.
ITNG
Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Tim Kerins, Paulo S. L. M. Barreto
2007 J jnl
A flexible processor for the characteristic 3 η
Int. J. High Perform. Syst. Archit.
Robert Ronan, Colin C. Murphy, Tim Kerins, Colm O'hEigeartaigh, Paulo S. L. M. Barreto
2007 J jnl
Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve.
J. Syst. Archit.
Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins
2007 — conf
Public-Key Cryptography for RFID-Tags.
PerCom Workshops
Lejla Batina, Jorge Guajardo, Tim Kerins, Nele Mentens, Pim Tuyls, Ingrid Verbauwhede
2007 J jnl
Versatile hardware architectures for GF(p
Integr.
Tim Kerins, William P. Marnane, Emanuel M. Popovici
2006 J jnl
An Elliptic Curve Processor Suitable For RFID-Tags.
IACR Cryptol. ePrint Arch.
Lejla Batina, Jorge Guajardo, Tim Kerins, Nele Mentens, Pim Tuyls, Ingrid Verbauwhede
2006 — conf
An Embedded Processor for a Pairing-Based Cryptosystem.
ITNG
Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins, William P. Marnane
2006 — conf
FPGA Implementation of a
ARC
Maurice Keller, Tim Kerins, Francis M. Crowe, William P. Marnane
2006 — conf
FPGA acceleration of the tate pairing in characteristic 2.
FPT
Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins
2006 J jnl
Hardware Implementation of the η
IACR Cryptol. ePrint Arch.
Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Tim Kerins, Paulo S. L. M. Barreto
2006 — conf
Security in Next Generation Consumer Electronic Devices.
ISSE
Tom Kan, Tim Kerins, Klaus Kursawe
2005 J jnl
A Dedicated Processor for the eta Pairing.
IACR Cryptol. ePrint Arch.
Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins, William P. Marnane
2005 A conf
Efficient Hardware for the Tate Pairing Calculation in Characteristic Three.
CHES
Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto
2005 J jnl
Efficient hardware for the Tate pairing calculation in characteristic three.
IACR Cryptol. ePrint Arch.
Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto
2005 B conf
FPGA Implementation of a GF(2
FPL
Maurice Keller, Tim Kerins, William P. Marnane
2004 B conf
Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes.
FPL
Tim Kerins, Emanuel M. Popovici, William P. Marnane
2004 J jnl
An FPGA implementation of a GF(p) ALU for encryption processors.
Microprocess. Microsystems
Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici
2004 — conf
Single-chip FPGA implementation of a cryptographic co-processor.
FPT
Francis M. Crowe, Alan Daly, Tim Kerins, William P. Marnane
2003 B conf
Fast Modular Division for Application in ECC on Reconfigurable Logic.
FPL
Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici
2002 B conf
Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2).
FPL
Tim Kerins, Emanuel M. Popovici, William P. Marnane, Patrick Fitzpatrick