Tim Fischer

33 papers A* 2A 3B 1C 2Journal 23Unranked 2
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators.
CoRR
Luca Colagrande, Lorenzo Leone, Chen Wu, Tim Fischer, Raphael Roth, Luca Benini
2025 A conf
AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors.
DATE
Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini
2025 J jnl
AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors.
CoRR
Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini
2025 J jnl
ControlPULPlet: A Flexible Real-time Multicore RISC-V Controller for 2.5-D Systems-in-Package.
IEEE Trans. Very Large Scale Integr. Syst.
Alessandro Ottaviano, Robert Balas, Tim Fischer, Thomas Benz, Andrea Bartolini, Luca Benini
2025 J jnl
FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support.
IEEE Trans. Very Large Scale Integr. Syst.
Tim Fischer, Michael Rogenmoser, Thomas Benz, Frank K. Gürkaynak, Luca Benini
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET.
IEEE J. Solid State Circuits
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET.
CoRR
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 C conf
TeraNOC: A Multi-Channel 32-Bit Fine-Grained, Hybrid Mesh-Crossbar Noc for Efficient Scale-Up of 1000+ Core Shared-L1-Memory Clusters.
ICCD
Yichao Zhang, Zexin Fu, Tim Fischer, Yinrong Li, Marco Bertuletti, Luca Benini
2025 J jnl
TeraNoC: A Multi-Channel 32-bit Fine-Grained, Hybrid Mesh-Crossbar NoC for Efficient Scale-up of 1000+ Core Shared-L1-Memory Clusters.
CoRR
Yichao Zhang, Zexin Fu, Tim Fischer, Yinrong Li, Marco Bertuletti, Luca Benini
2025 J jnl
Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond.
CoRR
Paul Scheffler, Thomas Benz, Tim Fischer, Lorenzo Leone, Sina Arjmandpour, Luca Benini
2024 J jnl
ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package.
CoRR
Alessandro Ottaviano, Robert Balas, Tim Fischer, Thomas Benz, Andrea Bartolini, Luca Benini
2024 J jnl
FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support.
CoRR
Tim Fischer, Michael Rogenmoser, Thomas Benz, Frank K. Gürkaynak, Luca Benini
2024 J jnl
MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products.
IEEE Trans. Emerg. Top. Comput.
Luca Bertaccini, Gianna Paulin, Matheus A. Cavalcante, Tim Fischer, Stefan Mach, Luca Benini
2024 — conf
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
VLSI Technology and Circuits
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 J jnl
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
CoRR
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 J jnl
Optimizing Foundation Model Inference on a Many-Tiny-Core Open-Source RISC-V Platform.
IEEE Trans. Circuits Syst. Artif. Intell.
Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini
2024 J jnl
Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform.
CoRR
Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini
2023 J jnl
7 μJ/inference end-to-end gesture recognition from dynamic vision sensor data using ternarized hybrid convolutional neural networks.
Future Gener. Comput. Syst.
Georg Rutishauser, Moritz Scherer, Tim Fischer, Luca Benini
2023 J jnl
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic.
IEEE Des. Test
Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini
2023 J jnl
FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic.
CoRR
Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini
2023 A* conf
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement.
DAC
Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
2023 A conf
ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers.
ISLPED
Gamze Islamoglu, Moritz Scherer, Gianna Paulin, Tim Fischer, Victor J. B. Jung, Angelo Garofalo, Luca Benini
2023 J jnl
ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers.
CoRR
Gamze Islamoglu, Moritz Scherer, Gianna Paulin, Tim Fischer, Victor J. B. Jung, Angelo Garofalo, Luca Benini
2023 A* conf
Sparse Hamming Graph: A Customizable Network-on-Chip Topology.
DAC
Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
2023 J jnl
TCN-CUTIE: A 1, 036-TOp/s/W, 2.72-µJ/Inference, 12.2-mW All-Digital Ternary Accelerator in 22-nm FDX Technology.
IEEE Micro
Moritz Scherer, Alfio Di Mauro, Tim Fischer, Georg Rutishauser, Luca Benini
2022 — conf
A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications.
COOL CHIPS
Moritz Scherer, Alfio Di Mauro, Georg Rutishauser, Tim Fischer, Luca Benini
2022 J jnl
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement.
CoRR
Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
2022 C conf
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores.
ARITH
Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini
2022 J jnl
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores.
CoRR
Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini
2022 J jnl
Sparse Hamming Graph: A Customizable Network-on-Chip Topology.
CoRR
Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
2022 J jnl
TCN-CUTIE: A 1036 TOp/s/W, 2.72 uJ/Inference, 12.2 mW All-Digital Ternary Accelerator in 22 nm FDX Technology.
CoRR
Moritz Scherer, Alfio Di Mauro, Tim Fischer, Georg Rutishauser, Luca Benini
2022 A conf
Ternarized TCN for $\mu \mathrm{J}/\text{Inference}$ Gesture Recognition from DVS Event Frames.
DATE
Georg Rutishauser, Moritz Scherer, Tim Fischer, Luca Benini
2019 B conf
Piepser: A Smart Wrist-Worn Variometer To Maximize The Paragliders Flytime.
SAS
Tim Fischer, Michael Ganz, Nicolas Baumann, Michele Magno