Tiantao Lu

12 papers A* 1A 2Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2019 J jnl
Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhiyuan Yang, Caleb Serafy, Tiantao Lu, Ankur Srivastava
2017 J jnl
Low-Power Clock Tree Synthesis for 3D-ICs.
ACM Trans. Design Autom. Electr. Syst.
Tiantao Lu, Ankur Srivastava
2017 A* conf
Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors.
DAC
Zhiyuan Yang, Caleb Serafy, Tiantao Lu, Ankur Srivastava
2017 J jnl
TSV-Based 3-D ICs: Design Methods and Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Sandeep Kumar Samal, Sung Kyu Lim, Ankur Srivastava
2016 — conf
Electromigration-aware placement for 3D-ICs.
ISQED
Tiantao Lu, Zhiyuan Yang, Ankur Srivastava
2016 — conf
Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction.
ISVLSI
Tiantao Lu, Zhiyuan Yang, Ankur Srivastava
2016 J jnl
Security and Vulnerability Implications of 3D ICs.
IEEE Trans. Multi Scale Comput. Syst.
Yang Xie, Chongxi Bao, Caleb Serafy, Tiantao Lu, Ankur Srivastava, Mark Tehranipoor
2016 A conf
Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs.
ISLPED
Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Ankur Srivastava
2015 — conf
Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs.
ACM Great Lakes Symposium on VLSI
Tiantao Lu, Ankur Srivastava
2015 J jnl
Modeling and Layout Optimization for Tapered TSVs.
IEEE Trans. Very Large Scale Integr. Syst.
Tiantao Lu, Ankur Srivastava
2014 A conf
Gated low-power clock tree synthesis for 3D-ICs.
ISLPED
Tiantao Lu, Ankur Srivastava
2013 — conf
Detailed electrical and reliability study of tapered TSVs.
3DIC
Tiantao Lu, Ankur Srivastava