Tiankai Su

11 papers A 1B 1C 2Journal 2Unranked 5
YearRankTypeTitle / Venue / Authors
2023 — conf
Formal Verification of Divider Circuits by Hardware Reduction.
SMACD
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
2020 — conf
Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach.
ISVLSI
Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski
2020 A conf
SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification.
DATE
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
2020 J jnl
Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Maciej J. Ciesielski, Tiankai Su, Atif Yasin, Cunxi Yu
2019 — conf
Formal Verification of Integer Dividers: Division by a Constant.
ISVLSI
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
2019 C conf
Functional Verification of Hardware Dividers using Algebraic Model.
VLSI-SoC
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
2019 J jnl
Spectral Approach to Verifying Non-linear Arithmetic Circuits.
CoRR
Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski
2019 — conf
Spectral approach to verifying non-linear arithmetic circuits.
ASP-DAC
Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski
2018 C conf
Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers.
ISCAS
Tiankai Su, Atif Yasin, Cunxi Yu, Maciej J. Ciesielski
2018 B conf
Rewriting Environment for Arithmetic Circuit Verification.
LPAR
Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski
2017 — conf
Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis.
ISVLSI
Tiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski