Tian-Sheuan Chang

168 papers A* 2A 4C 37Misc 1Journal 85Unranked 38

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Low-Power Vision Transformer Accelerator With Hardware-Aware Pruning and Optimized Dataflow. IEEE Trans. Circuits Syst. I Regul. Pap. Ching-Lin Hsiung, Tian-Sheuan Chang
2025	J	`jnl`	A 71.2-μW Speech Recognition Accelerator with Recurrent Spiking Neural Network. CoRR Chih-Chyau Yang, Tian-Sheuan Chang
2025	C	`conf`	A Low-Power Sparse Deep Learning Accelerator with Optimized Data Reuse. ISCAS Kai-Chieh Hsu, Tian-Sheuan Chang
2025	J	`jnl`	A Low-Power Sparse Deep Learning Accelerator with Optimized Data Reuse. CoRR Kai-Chieh Hsu, Tian-Sheuan Chang
2025	J	`jnl`	A Low-Power Streaming Speech Enhancement Accelerator For Edge Devices. CoRR Ci-Hao Wu, Tian-Sheuan Chang
2025	C	`conf`	An Efficient Data Reuse with Tile-Based Adaptive Stationary for Transformer Accelerators. ISCAS Tseng-Jen Li, Tian-Sheuan Chang
2025	J	`jnl`	An Efficient Data Reuse with Tile-Based Adaptive Stationary for Transformer Accelerators. CoRR Tseng-Jen Li, Tian-Sheuan Chang
2025	J	`jnl`	CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. CoRR Yan-Cheng Guo, Tian-Sheuan Chang, Chih-Sheng Lin, Bo-Cheng Chiou, Chih-Ming Lai, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang
2025	J	`jnl`	Computing-In-Memory Aware Model Adaption For Edge Devices. CoRR Ming-Han Lin, Tian-Sheuan Chang
2025	J	`jnl`	Dynamic Gradient Sparse Update for Edge Training. CoRR I-Hsuan Li, Tian-Sheuan Chang
2025	J	`jnl`	ESSR: An 8K@30FPS Super-Resolution Accelerator With Edge Selective Network. CoRR Chih-Chia Hsu, Tian-Sheuan Chang
2025	J	`jnl`	Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering Techniques. CoRR Qun-Kai Lin, Cheng Hsu, Tian-Sheuan Chang
2025	C	`conf`	Hardware Efficient Accelerator for Spiking Transformer With Reconfigurable Parallel Time Step Computing. ISCAS Bo-Yu Chen, Tian-Sheuan Chang
2025	J	`jnl`	Hardware Efficient Accelerator for Spiking Transformer With Reconfigurable Parallel Time Step Computing. CoRR Bo-Yu Chen, Tian-Sheuan Chang
2025	J	`jnl`	Low Power Vision Transformer Accelerator with Hardware-Aware Pruning and Optimized Dataflow. CoRR Ching-Lin Hsiung, Tian-Sheuan Chang
2025	J	`jnl`	VESTA: A Versatile SNN-Based Transformer Accelerator with Unified PEs for Multiple Computational Layers. CoRR Ching-Yao Chen, Meng-Chieh Chen, Tian-Sheuan Chang
2024	J	`jnl`	A 71.2-μW Speech Recognition Accelerator With Recurrent Spiking Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. Chih-Chyau Yang, Tian-Sheuan Chang
2024	J	`jnl`	A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices. IEEE Open J. Circuits Syst. Ci-Hao Wu, Tian-Sheuan Chang
2024	A	`conf`	A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application. DATE Kuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang
2024	J	`jnl`	ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator With Decoupled Asymmetric Convolution. IEEE Trans. Circuits Syst. I Regul. Pap. Tun-Hao Yang, Tian-Sheuan Chang
2024	J	`jnl`	ASC: Adaptive Scale Feature Map Compression for Deep Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. Yuan Yao, Tian-Sheuan Chang
2024	C	`conf`	CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. ISCAS Yan-Cheng Guo, Tian-Sheuan Chang, Chih-Sheng Lin, Bo-Cheng Chiou, Chih-Ming Lai, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang
2024	C	`conf`	Dynamic Gradient Sparse Update for Edge Training. ISCAS I-Hsuan Li, Tian-Sheuan Chang
2024	J	`jnl`	ESSR: An 8K@30FPS Super-Resolution Accelerator With Edge Selective Network. IEEE Trans. Circuits Syst. I Regul. Pap. Chih-Chia Hsu, Tian-Sheuan Chang
2024	—	`conf`	Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security. VLSI Technology and Circuits Chih-Sheng Lin, Bo-Cheng Chiou, Yin-Jia Yang, Jian-Wei Su, Kuo-Hua Tseng, Yun-Ting Ho, Chih-Ming Lai, Sih-Han Li, Tian-Sheuan Chang, Shan-Ming Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
2024	—	`conf`	Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering Techniques. APCCAS Qun-Kai Lin, Cheng Hsu, Tian-Sheuan Chang
2024	J	`jnl`	IQNet: Image Quality Assessment Guided Just Noticeable Difference Prefiltering for Versatile Video Coding. IEEE Open J. Circuits Syst. Yu-Han Sun, Chiang Lo-Hsuan Lee, Tian-Sheuan Chang
2024	—	`conf`	VESTA: A Versatile SNN-Based Transformer Accelerator with Unified PEs for Multiple Computational Layers. APCCAS Ching-Yao Chen, Meng-Chieh Chen, Tian-Sheuan Chang
2023	J	`jnl`	A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation. CoRR Chih-Chyau Yang, Tian-Sheuan Chang
2023	J	`jnl`	A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation. IEEE Trans. Very Large Scale Integr. Syst. Chih-Chyau Yang, Tian-Sheuan Chang
2023	J	`jnl`	ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator with Decoupled Asymmetric Convolution. CoRR Tun-Hao Yang, Tian-Sheuan Chang
2023	J	`jnl`	ASC: Adaptive Scale Feature Map Compression for Deep Neural Network. CoRR Yuan Yao, Tian-Sheuan Chang
2023	C	`conf`	FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices. ISCAS Yan-Cheng Guo, Wei-Tien Lin, Tuo-Hung Hou, Tian-Sheuan Chang
2023	J	`jnl`	IQNet: Image Quality Assessment Guided Just Noticeable Difference Prefiltering For Versatile Video Coding. CoRR Yu-Han Sun, Chiang Lo-Hsuan Lee, Tian-Sheuan Chang
2023	J	`jnl`	Memory Bandwidth Efficient Design for Super-Resolution Accelerators With Structure Adaptive Fusion and Channel-Aware Addressing. IEEE Trans. Very Large Scale Integr. Syst. An-Jung Huang, Jo-Hsuan Hung, Tian-Sheuan Chang
2022	J	`jnl`	A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization. IEEE Trans. Very Large Scale Integr. Syst. Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou
2022	J	`jnl`	A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization. CoRR Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou
2022	J	`jnl`	A Real Time 1280x720 Object Detection Chip With 585MB/s Memory Traffic. CoRR Kuo-Wei Chang, Hsu-Tung Shih, Tian-Sheuan Chang, Shang-Hong Tsai, Chih-Chyau Yang, Chien-Ming Wu, Chun-Ming Huang
2022	C	`conf`	A Real Time Super Resolution Accelerator with Tilted Layer Fusion. ISCAS An-Jung Huang, Kai-Chieh Hsu, Tian-Sheuan Chang
2022	J	`jnl`	A Real Time Super Resolution Accelerator with Tilted Layer Fusion. CoRR An-Jung Huang, Kai-Chieh Hsu, Tian-Sheuan Chang
2022	J	`jnl`	A Real-Time 1280 × 720 Object Detection Chip With 585 MB/s Memory Traffic. IEEE Trans. Very Large Scale Integr. Syst. Kuo-Wei Chang, Hsu-Tung Shih, Tian-Sheuan Chang, Shang-Hong Tsai, Chih-Chyau Yang, Chien-Ming Wu, Chun-Ming Huang
2022	J	`jnl`	A Secure File Sharing System Based on IPFS and Blockchain. CoRR Hsiao-Shan Huang, Tian-Sheuan Chang, Jhih-Yi Wu
2022	—	`conf`	An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. VLSI-DAT Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
2022	C	`conf`	BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention. ISCAS Dun-Hao Yang, Tian-Sheuan Chang
2022	J	`jnl`	BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention. CoRR Dun-Hao Yang, Tian-Sheuan Chang
2022	J	`jnl`	Efficient Accelerator for Dilated and Transposed Convolution with Decomposition. CoRR Kuo-Wei Chang, Tian-Sheuan Chang
2022	J	`jnl`	Hardware-Robust In-RRAM-Computing for Object Detection. CoRR Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
2022	J	`jnl`	Hardware-Robust In-RRAM-Computing for Object Detection. IEEE J. Emerg. Sel. Topics Circuits Syst. Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
2022	J	`jnl`	IMU Based Deep Stride Length Estimation With Self-Supervised Learning. CoRR Jien-De Sui, Tian-Sheuan Chang
2022	C	`conf`	PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting. ISCAS Shu-Hung Kuo, Tian-Sheuan Chang
2022	J	`jnl`	PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting. CoRR Shu-Hung Kuo, Tian-Sheuan Chang
2022	J	`jnl`	Pre-RTL DNN Hardware Evaluator With Fused Layer Support. CoRR Chih-Chyau Yang, Tian-Sheuan Chang
2022	J	`jnl`	Real Time On Sensor Gait Phase Detection with 0.5KB Deep Learning Model. CoRR Yian Chen, Jien-De Sui, Tian-Sheuan Chang
2022	J	`jnl`	Real-Time Wearable Gait Phase Segmentation For Running And Walking. CoRR Jien-De Sui, Wei-Han Chen, Tzyy-Yuang Shiang, Tian-Sheuan Chang
2022	—	`conf`	Row-wise Accelerator for Vision Transformer. AICAS Hong-Yi Wang, Tian-Sheuan Chang
2022	J	`jnl`	Row-wise Accelerator for Vision Transformer. CoRR Hong-Yi Wang, Tian-Sheuan Chang
2022	J	`jnl`	Sparse Compressed Spiking Neural Network Accelerator for Object Detection. CoRR Hong-Han Lien, Tian-Sheuan Chang
2022	J	`jnl`	Sparse Compressed Spiking Neural Network Accelerator for Object Detection. IEEE Trans. Circuits Syst. I Regul. Pap. Hong-Han Lien, Tian-Sheuan Chang
2022	J	`jnl`	VSA: Reconfigurable Vectorwise Spiking Neural Network Accelerator. CoRR Hong-Han Lien, Chung-Wei Hsu, Tian-Sheuan Chang
2022	J	`jnl`	VSCNN: Convolution Neural Network Accelerator With Vector Sparsity. CoRR Kuo-Wei Chang, Tian-Sheuan Chang
2022	J	`jnl`	VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network. CoRR Kuo-Wei Chang, Tian-Sheuan Chang
2022	J	`jnl`	Zebra: Memory Bandwidth Reduction for CNN Accelerators With Zero Block Regularization of Activation Maps. CoRR Hsu-Tung Shih, Tian-Sheuan Chang
2021	—	`conf`	A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. A-SSCC Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou
2021	—	`conf`	Pre-RTL DNN Hardware Evaluator With Fused Layer Support. ISOCC Chih-Chyau Yang, Tian-Sheuan Chang
2021	C	`conf`	VSA: Reconfigurable Vectorwise Spiking Neural Network Accelerator. ISCAS Hong-Han Lien, Chung-Wei Hsu, Tian-Sheuan Chang
2020	—	`conf`	A Secure File Sharing System Based on IPFS and Blockchain. IECC Hsiao-Shan Huang, Tian-Sheuan Chang, Jhih-Yi Wu
2020	C	`conf`	Efficient Accelerator for Dilated and Transposed Convolution with Decomposition. ISCAS Kuo-Wei Chang, Tian-Sheuan Chang
2020	J	`jnl`	Image Synthesis With Efficient Defocus Blur for Stereoscopic Displays. IEEE Access Yi-Chun Chen, Tian-Sheuan Chang
2020	—	`conf`	Real Time On Sensor Gait Phase Detection with 0.5KB Deep Learning Model. ICCE-TW Yian Chen, Jien-De Sui, Tian-Sheuan Chang
2020	C	`conf`	Real-Time Wearable Gait Phase Segmentation for Running And Walking. ISCAS Jien-De Sui, Wei-Han Chen, Tzyy-Yuang Shiang, Tian-Sheuan Chang
2020	J	`jnl`	VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. Kuo-Wei Chang, Tian-Sheuan Chang
2020	C	`conf`	Zebra: Memory Bandwidth Reduction for CNN Accelerators with Zero Block Regularization of Activation Maps. ISCAS Hsu-Tung Shih, Tian-Sheuan Chang
2019	A*	`conf`	NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge. DAC Chih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou
2019	C	`conf`	VSCNN: Convolution Neural Network Accelerator with Vector Sparsity. ISCAS Kuo-Wei Chang, Tian-Sheuan Chang
2018	—	`conf`	A Scoping Study on the Development of an Interactive Upper-Limb Rehabilitation System Framework for Patients with Stroke. HCI (8) Kevin C. Tseng, Alice M. K. Wong, Chung-Yu Wu, Tian-Sheuan Chang, Yu-Cheng Pei, Jean-Lon Chen
2018	—	`conf`	End-to-end hardware accelerator for deep convolutional neural network. VLSI-DAT Tian-Sheuan Chang
2018	J	`jnl`	Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse. IEEE J. Emerg. Sel. Topics Circuits Syst. Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou
2017	C	`conf`	Fast rate distortion optimization with adaptive context group modeling for HEVC. ISCAS Hung-Cheng Chen, Tian-Sheuan Chang
2017	J	`jnl`	Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse. CoRR Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou
2016	J	`jnl`	A QFHD 30-frames/s HEVC Decoder Design. IEEE Trans. Circuits Syst. Video Technol. Pai-Tse Chiang, Yi-Ching Ting, Hsuan-ku Chen, Shiau-Yu Jou, I-Wen Chen, Hang-Chiu Fang, Tian-Sheuan Chang
2016	C	`conf`	Fast intra prediction algorithm and design for high efficiency video coding. ISCAS Han-Chiou Fang, Hung-Cheng Chen, Tian-Sheuan Chang
2016	—	`conf`	Perceptual oriented depth cue enhancement for stereoscopic view synthesis. 3DTV-Conference Yi-Chun Chen, Tian-Sheuan Chang
2015	C	`conf`	A hardware-efficient deblocking filter design for HEVC. ISCAS Chih-Chung Fang, I-Wen Chen, Tian-Sheuan Chang
2015	J	`jnl`	Fast Motion Estimation Algorithm and Design for Real Time QFHD High Efficiency Video Coding. IEEE Trans. Circuits Syst. Video Technol. Shiaw-Yu Jou, Shan-Jung Chang, Tian-Sheuan Chang
2014	J	`jnl`	Analysis and implementation of low-power perceptual multiband noise reduction for the hearing aids application. IET Circuits Devices Syst. Cheng-Wen Wei, Cheng-Chun Tsai, FanJiang Yi, Tian-Sheuan Chang, Shyh-Jye Jou
2014	J	`jnl`	Correction to "Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing". IEEE ACM Trans. Audio Speech Lang. Process. Yi FanChiang, Cheng-Wen Wei, Yi-Le Meng, Yu-Wen Lin, Shyh-Jye Jou, Tian-Sheuan Chang
2014	C	`conf`	Gradient-based PU size selection for HEVC intra prediction. ISCAS Yi-Ching Ting, Tian-Sheuan Chang
2014	J	`jnl`	Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing. IEEE ACM Trans. Audio Speech Lang. Process. Yi FanChiang, Cheng-Wen Wei, Yi-Le Meng, Yu-Wen Lin, Shyh-Jye Jou, Tian-Sheuan Chang
2014	—	`conf`	Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. SoCC Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang, Wei Hwang
2013	J	`jnl`	135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder. IEEE Trans. Very Large Scale Integr. Syst. Gwo-Long Li, Tzu-yu Chen, Meng-Wei Shen, Meng-Hsun Wen, Tian-Sheuan Chang
2013	C	`conf`	A reconfigurable inverse transform architecture design for HEVC decoder. ISCAS Pai-Tse Chiang, Tian-Sheuan Chang
2013	J	`jnl`	Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications. IEEE Trans. Very Large Scale Integr. Syst. Jui-Hung Hsieh, Tian-Sheuan Chang
2013	J	`jnl`	An Efficient Mode Preselection Algorithm for Fractional Motion Estimation in H.264/AVC Scalable Video Extension. IEEE Trans. Circuits Syst. Video Technol. Gwo-Long Li, Tian-Sheuan Chang
2013	J	`jnl`	Fast SIFT Design for Real-Time Visual Feature Extraction. IEEE Trans. Image Process. Liang-Chi Chiu, Tian-Sheuan Chang, Jiun-Yen Chen, Nelson Yen-Chung Chang
2013	—	`conf`	Fast prediction unit selection for HEVC fractional pel motion estimation design. SiPS Shiau-Yu Jou, Tian-Sheuan Chang
2013	C	`conf`	Fast zero block detection and early CU termination for HEVC Video Coding. ISCAS Pai-Tse Chiang, Tian-Sheuan Chang
2013	—	`ch.`	Real-Time Disparity Estimation Engine for High-Definition 3 DTV Applications. Emerging Technologies for 3D Video Yu-Cheng Tseng, Tian-Sheuan Chang
2012	J	`jnl`	A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder. IEEE Trans. Circuits Syst. Video Technol. Gwo-Long Li, Yu-Chen Chen, Yuan-Hsin Liao, Po-Yuan Hsu, Meng-Hsun Wen, Tian-Sheuan Chang
2012	J	`jnl`	A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video. IEEE Trans. Circuits Syst. Video Technol. Yuan-Hsin Liao, Gwo-Long Li, Tian-Sheuan Chang
2012	J	`jnl`	A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder. IEEE Trans. Circuits Syst. Video Technol. Yuan-Hsin Liao, Gwo-Long Li, Tian-Sheuan Chang
2012	C	`conf`	A high throughput CAVLC design for HEVC. ISCAS Hsuan-ku Chen, Tian-Sheuan Chang
2012	—	`conf`	A lossless embedded compression codec engine for HD video decoding. VLSI-DAT Liang-Chi Chiu, Tian-Sheuan Chang
2012	C	`conf`	A low complexity speech coder for binaural communication in hearing aids. ISCAS Shuo-Wen Hsu, Tian-Sheuan Chang
2012	—	`conf`	A low-power body-channel communication system for binaural hearing aids. BioCAS Jou-Ling Chen, Jhih-Cing Sun, Yi-Hung Shen, Tzu-Hsien Sang, Tian-Sheuan Chang, Shyh-Jye Jou
2012	C	`conf`	Fast disparity estimation for 3DTV applications. VCIP Yu-Cheng Tseng, Tian-Sheuan Chang
2012	—	`conf`	Fast intra prediction algorithm with transform domain edge detection for HEVC. APCCAS Yi-Ching Ting, Tian-Sheuan Chang
2012	J	`jnl`	Sub µW Noise Reduction for CIC Hearing Aids. IEEE Trans. Very Large Scale Integr. Syst. Cheng-Wen Wei, Sheng-Jie Su, Tian-Sheuan Chang, Shyh-Jye Jou
2011	J	`jnl`	A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering. IEEE Trans. Image Process. Yu-Cheng Tseng, Po-Hsiung Hsu, Tian-Sheuan Chang
2011	C	`conf`	A 94fps view synthesis engine for HD1080p video. VCIP Fu-Jen Chang, Yu-Cheng Tseng, Tian-Sheuan Chang
2011	—	`conf`	An efficient mode pre-selection algorithm for H.264/AVC scalable video extension fractional motion estimation. DSP Gwo-Long Li, Tian-Sheuan Chang
2011	—	`conf`	Bandwidth-constrained motion estimation for real-time mobile video application. DSP Jui-Hung Hsieh, Tian-Sheuan Chang
2011	—	`conf`	Fast algorithm for local stereo matching in disparity estimation. DSP Yu-Cheng Tseng, Tian-Sheuan Chang
2011	J	`jnl`	Memory bandwidth-scalable motion estimation for mobile video coding. EURASIP J. Adv. Signal Process. Jui-Hung Hsieh, Wei-Cheng Tai, Tian-Sheuan Chang
2011	J	`jnl`	VLSI Architecture for Real-Time HD1080p View Synthesis Engine. IEEE Trans. Circuits Syst. Video Technol. Ying-Rung Horng, Yu-Cheng Tseng, Tian-Sheuan Chang
2010	C	`conf`	A high throughput VLSI design with hybrid memory architecture for H.264/AVC CABAC decoder. ISCAS Yuan-Hsin Liao, Gwo-Long Li, Tian-Sheuan Chang
2010	J	`jnl`	Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight. IEEE Trans. Circuits Syst. Video Technol. Nelson Yen-Chung Chang, Tsung-Hsien Tsai, Po-Hsiung Hsu, Yi-Chun Chen, Tian-Sheuan Chang
2010	J	`jnl`	Architecture Design of Belief Propagation for Real-Time Disparity Estimation. IEEE Trans. Circuits Syst. Video Technol. Yu-Cheng Tseng, Tian-Sheuan Chang
2010	C	`conf`	Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension. ISCAS Yu-Chen Chen, Gwo-Long Li, Tian-Sheuan Chang
2010	C	`conf`	Fast stereo matching with predictive search range. PCS Yu-Cheng Tseng, Po-Hsiung Hsu, Tian-Sheuan Chang
2010	C	`conf`	Low memory cost bilateral filtering using stripe-based sliding integral histogram. ISCAS Po-Hsiung Hsu, Yu-Cheng Tseng, Tian-Sheuan Chang
2010	—	`conf`	Perceptual multiband spectral subtraction for noise reduction in hearing aids. APCCAS Cheng-Wen Wei, Cheng-Chun Tsai, Tian-Sheuan Chang, Shyh-Jye Jou
2010	J	`jnl`	RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design With On-Demand Data Access. IEEE Trans. Circuits Syst. Video Technol. Gwo-Long Li, Tian-Sheuan Chang
2010	C	`conf`	Stereoscopic images generation with directional Gaussian filter. ISCAS Ying-Rung Horng, Yu-Cheng Tseng, Tian-Sheuan Chang
2009	J	`jnl`	A 140-MHz 94 K Gates HD1080p 30-Frames/s Intra-Only Profile H.264 Encoder. IEEE Trans. Circuits Syst. Video Technol. Yu-Kun Lin, Chun-Wei Ku, De-Wei Li, Tian-Sheuan Chang
2009	C	`conf`	A Memory Efficient Fine Grain Scalability Coefficient Encoding Method for H.264/AVC Scalable Video Extension. ISCAS Meng-Wei Shen, Gwo-Long Li, Tian-Sheuan Chang
2009	J	`jnl`	Analysis of shared-link AXI. IET Comput. Digit. Tech. Nelson Yen-Chung Chang, Ying-Ze Liao, Tian-Sheuan Chang
2009	A	`conf`	Bandwidth-rate-distortion optimized motion estimation. ICME Wei-Cheng Tai, Gwo-Long Li, Tian-Sheuan Chang
2009	C	`conf`	Low-memory Cost Belief Propagation Architecture for Disparity Estimation. ISCAS Yu-Cheng Tseng, Nelson Yen-Chung Chang, Tian-Sheuan Chang
2009	C	`conf`	Memory Analysis for H.264/AVC Scalable Extension Encoder. ISCAS Tzu-yu Chen, Gwo-Long Li, Tian-Sheuan Chang
2008	—	`conf`	A 242mW 10mm ISSCC Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang
2008	A*	`conf`	A 242mW, 10mm DAC Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang
2008	J	`jnl`	A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video. IEEE Trans. Circuits Syst. I Regul. Pap. Yu-Kun Lin, Chia-Chun Lin, Tzu-Yun Kuo, Tian-Sheuan Chang
2008	J	`jnl`	Adaptive De-Interlacing With Robust Overlapped Block Motion Compensation. IEEE Trans. Circuits Syst. Video Technol. Sin-Bor Wang, Tian-Sheuan Chang
2008	—	`conf`	Analysis of color space and similarity measure impact on stereo block matching. APCCAS Nelson Yen-Chung Chang, Yu-Cheng Tseng, Tian-Sheuan Chang
2008	J	`jnl`	Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding. IEEE Trans. Circuits Syst. Video Technol. Hui-Cheng Hsu, Kun-Bin Lee, Nelson Yen-Chung Chang, Tian-Sheuan Chang
2008	—	`conf`	Block-based belief propagation with in-place message updating for stereo vision. APCCAS Yu-Cheng Tseng, Nelson Yen-Chung Chang, Tian-Sheuan Chang
2008	C	`conf`	Data reuse analysis of local stereo matching. ISCAS Tsung-Hsien Tsai, Nelson Yen-Chung Chang, Tian-Sheuan Chang
2008	C	`conf`	ISID : In-order scan and indexed diffusion segmentation algorithm for stereo vision. ISCAS Jing-Chu Chan, Nelson Yen-Chung Chang, Tian-Sheuan Chang
2007	—	`conf`	A 61MHz 72K Gates 1280x720 30FPS H.264 Intra Encoder. ICASSP (2) De-Wei Li, Chun-Wei Ku, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang
2007	J	`jnl`	A Fast Algorithm and Its VLSI Architecture for Fractional Motion Estimation for H.264/MPEG-4 AVC Video Coding. IEEE Trans. Circuits Syst. Video Technol. Yu-Jen Wang, Chao-Chung Cheng, Tian-Sheuan Chang
2007	—	`conf`	A Low Cost Context Adaptive Arithmetic Coder for H.264/MPEG-4 AVC Video Coding. ICASSP (2) Jian-Long Chen, Yu-Kun Lin, Tian-Sheuan Chang
2007	A	`conf`	Low Memory Cost Block-Based Belief Propagation for Stereo Correspondence. ICME Yu-Cheng Tseng, Nelson Yen-Chung Chang, Tian-Sheuan Chang
2007	—	`conf`	Optimal Data Mapping for Motion Compensation in H.264 Video Decoding. SiPS Guo-Shiuan Yu, Tian-Sheuan Chang
2007	—	`conf`	PMRME: A Parallel Multi-Resolution Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding. ICASSP (2) Chia-Chun Lin, Yu-Kun Lin, Tian-Sheuan Chang
2007	A	`conf`	Real-Time DSP Implementation on Local Stereo Matching. ICME Nelson Yen-Chung Chang, Ting-Min Lin, Tsung-Hsien Tsai, Yu-Cheng Tseng, Tian-Sheuan Chang
2007	—	`conf`	SIFME: A Single Iteration Fractional-Pel Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding. ICASSP (1) Tzu-Yun Kuo, Yu-Kun Lin, Tian-Sheuan Chang
2006	C	`conf`	A 1280×720 pixels 30 frames/s H.264/MPEG-4 AVC intra encoder. ISCAS Chao-Chung Cheng, Chun-Wei Ku, Tian-Sheuan Chang
2006	—	`conf`	A Display Order Oriented Scalable Video Decoder. APCCAS Jia-Bin Huang, Yu-Kun Lin, Tian-Sheuan Chang
2006	—	`conf`	A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding. APCCAS Chia-Chun Lin, Yu-Kun Lin, Tian-Sheuan Chang
2006	J	`jnl`	A High-Definition H.264/AVC Intra-Frame Codec IP for Digital Video and Still Camera Applications. IEEE Trans. Circuits Syst. Video Technol. C.-W. Ku, C.-C. Cheng, G.-S. Yu, M.-C. Tsai, Tian-Sheuan Chang
2006	—	`conf`	A Memory Bandwidth Optimized Interpolator for Motion Compensation in the H.264 Video Decoding. APCCAS Tzu-Yun Kuo, Yu-Kun Lin, Tian-Sheuan Chang
2006	C	`conf`	A fast fractional pel motion estimation algorithm for H.264/MPEG-4 AVC. ISCAS Yu-Jen Wang, Chao-Chung Cheng, Tian-Sheuan Chang
2006	C	`conf`	A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264. ISCAS Guo-Shiuan Yu, Tian-Sheuan Chang
2006	—	`conf`	Algorithms and DSP implementation of H.264/AVC. ASP-DAC Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, Hsueh-Ming Hang
2006	J	`jnl`	An Efficient Binary Motion Estimation Algorithm and its Architecture for MPEG-4 Shape Encoding. IEEE Trans. Circuits Syst. Video Technol. Esam A. Al Qaralleh, Tian-Sheuan Chang, Kun-Bin Lee
2006	J	`jnl`	An in-place architecture for the deblocking filter in H.264/AVC. IEEE Trans. Circuits Syst. II Express Briefs Chao-Chung Cheng, Tian-Sheuan Chang, Kun-Bin Lee
2006	J	`jnl`	Combined Frame Memory Motion Compensation for Video Coding. IEEE Trans. Circuits Syst. Video Technol. Nelson Yen-Chung Chang, Tian-Sheuan Chang
2006	J	`jnl`	Fast Variable Block Size Motion Estimation by Adaptive Early Termination. IEEE Trans. Circuits Syst. Video Technol. Esam A. Al Qaralleh, Tian-Sheuan Chang
2006	—	`conf`	High Performance Context Adaptive Variable Length Coding Encoder for MPEG-4 AVC/H.264 Video Coding. APCCAS Min-Chi Tsai, Tian-Sheuan Chang
2005	—	`conf`	A bandwidth efficient subsampling-based block matching architecture for motion estimation. ASP-DAC Hao-Yun Chin, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang
2005	J	`jnl`	A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. IEEE Trans. Circuits Syst. Video Technol. Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen
2005	—	`conf`	Combined frame memory architecture for motion compensation in video decoding. ISCAS (2) Nelson Yen-Chung Chang, Tian-Sheuan Chang
2005	—	`conf`	Fast block type decision algorithm for intra prediction in H.264 FRext. ICIP (1) Yu-Kun Lin, Tian-Sheuan Chang
2005	—	`conf`	Fast three step intra prediction algorithm for 4×4 blocks in H.264. ISCAS (2) Chao-Chung Cheng, Tian-Sheuan Chang
2005	J	`jnl`	The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning. IEICE Trans. Electron. Hun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo, Chein-Wei Jen
2002	J	`jnl`	On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture. IEEE Trans. Circuits Syst. Video Technol. Jen-Chieh Tuan, Tian-Sheuan Chang, Chein-Wei Jen
2000	J	`jnl`	A simple processor core design for DCT/IDCT. IEEE Trans. Circuits Syst. Video Technol. Tian-Sheuan Chang, Chin-Sheng Kung, Chein-Wei Jen
1998	Misc	`conf`	Low power FIR filter realization with differential coefficients and input. ICASSP Tian-Sheuan Chang, Chein-Wei Jen