Thucydides Xanthopoulos

18 papers A* 1A 2Journal 5Unranked 9

Year	Rank	Type	Title / Venue / Authors
2012	—	`conf`	A 32-core RISC microprocessor with network accelerators, power management and testability features. ISSCC Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, David Carlson, Vishnu Yalala, Thucydides Xanthopoulos, Scott E. Meninger, Ethan Crain, Mark Spaeth, Akin Aina, Suresh Balasubramanian, Joe Vulih, Pragati Tiwary, David Lin, Richard Kessler, Bruce Fishbein, Anil Jain
2012	J	`jnl`	Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring. IEEE Trans. Very Large Scale Integr. Syst. Dongwan Ha, Kyoungho Woo, Scott E. Meninger, Thucydides Xanthopoulos, Ethan Crain, Donhee Ham
2009	—	`conf`	Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring. ISSCC Kyoungho Woo, Scott E. Meninger, Thucydides Xanthopoulos, Ethan Crain, Dongwan Ha, Donhee Ham
2008	—	`conf`	Can Multicore Integration Justify the Increased Cost of Process Scalling? ISSCC Thucydides Xanthopoulos, Don Draper
2007	—	`conf`	Clocking. ISSCC Thucydides Xanthopoulos, Atila Alvandpour
2006	—	`conf`	A 16-Core RISC Microprocessor with Network Extensions. ISSCC Vishnu Yalala, Derek Brasili, David Carlson, Adam Hughes, Anil Jain, Tim Kiszely, Kolar Kodandapani, Anand Varadharajan, Thucydides Xanthopoulos
2005	J	`jnl`	Introduction to the Special Issue on the ISSCC2004. IEEE J. Solid State Circuits Georgios K. Konstadinidis, Anantha P. Chandrakasan, Sreedhar Natarajan, Thucydides Xanthopoulos
2000	J	`jnl`	A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization. IEEE J. Solid State Circuits Thucydides Xanthopoulos, Anantha P. Chandrakasan
1999	J	`jnl`	A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning. IEEE Trans. Very Large Scale Integr. Syst. Seong-Hwan Cho, Thucydides Xanthopoulos, Anantha P. Chandrakasan
1999	J	`jnl`	A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity. IEEE J. Solid State Circuits Thucydides Xanthopoulos, Anantha P. Chandrakasan
1999	—	`—`	Low power data-dependent transform video and still image coding. Thucydides Xanthopoulos
1999	A	`conf`	Power scalable processing using distributed arithmetic. ISLPED Rajeevan Amirtharajah, Thucydides Xanthopoulos, Anantha P. Chandrakasan
1998	—	`conf`	An ultra low power variable length decoder for MPEG-2 exploiting codeword distribution. CICC Seong-Hwan Cho, Thucydides Xanthopoulos, Anantha P. Chandrakasan
1997	A*	`conf`	Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT. DAC Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha P. Chandrakasan
1996	A	`conf`	Data driven signal processing: an approach for energy efficient computing. ISLPED Anantha P. Chandrakasan, Vadim Gutnik, Thucydides Xanthopoulos
1995	—	`conf`	Low-latency plesiochronous data retiming. ARVLSI Larry R. Dennison, William J. Dally, Thucydides Xanthopoulos
1994	—	`conf`	Architecture and implementation of the reliable router. Hot Interconnects William J. Dally, Larry R. Dennison, David Money Harris, Kinhong Kan, Thucydides Xanthopoulos
1994	—	`conf`	The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers. PCRCW William J. Dally, Larry R. Dennison, David Money Harris, Kinhong Kan, Thucydides Xanthopoulos