Thomas Wild - RankMe

144 papers A* 1A 10B 5C 20Misc 4Journal 32Unranked 68

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	An Approach for Automotive ECU Diagnosis via Ethernet Snooping & Microcontroller Tracing. WiPiEC Journal Zafer Attal, Matthias Ernst, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf
2025	A	`conf`	HiPerNoC: A High-Performance Network-an-Chip for Flexible and Scalable FPGA-Based SmartNICs. DATE Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf
2025	J	`jnl`	Rule-Based Reinforcement Learning on FPGA for QoS-Aware Dynamic Frequency Scaling. IEEE Trans. Very Large Scale Integr. Syst. Florian Maurer, Michael Meidinger, Yiming Lu, Matthias Schlemmer, Thomas Hallermeier, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf
2024	A	`conf`	EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. DATE Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jürgen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer
2024	—	`conf`	EPIC-Q: Equivalent-Policy Invariant Comparison Enhanced Transfer Q-learning for Run-Time SoC Performance-Power Optimization. SAMOS Anmol Surhonne, Haitham S. Fawzi, Florian Maurer, Oliver Lenke, Michael Meidinger, Thomas Wild, Andreas Herkersdorf
2024	C	`conf`	FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar. DSD Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf
2024	J	`jnl`	FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar. CoRR Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf
2024	C	`conf`	FlexRoute: A Fast, Flexible and Priority-Aware Packet-Processing Design. PDP Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf
2024	—	`conf`	HASIIL: Hardware-Assisted Scheduling to Improve IPC Latency in Linux. CF Tim Twardzik, Lars Nolte, Camille Jalier, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf
2024	—	`conf`	HW-EPOLL: Hardware-Assisted User Space Event Notification for Epoll Syscall. SAMOS Lars Nolte, Tim Twardzik, Camille Jalier, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf
2024	J	`jnl`	HW-FUTEX: Hardware-Assisted Futex Syscall. IEEE Trans. Very Large Scale Integr. Syst. Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf
2024	—	`conf`	Hardware Assist for Linux IPC on an FPGA Platform. CF Lars Nolte, Tim Twardzik, Camille Jalier, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf
2024	—	`conf`	QoS-Aware Dynamic Frequency Scaling for Mixed-Critical Systems based on Shielded Reinforcement Learning. NorCAS Florian Maurer, Michael Meidinger, Yiming Lu, Thomas Hallermeier, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf
2024	—	`conf`	XCS with dynamic sized experience replay for memory constrained applications. GECCO Companion Anmol Surhonne, Manuel Wensauer, Florian Maurer, Thomas Wild, Andreas Herkersdorf
2024	C	`conf`	ecoNIC: Saving Energy Through SmartNIC-Based Load Balancing of Mixed-Critical Ethernet Traffic. DSD Franz Biersack, Marco Liess, Markus Absmann, Fabiana Lotter, Thomas Wild, Andreas Herkersdorf
2023	—	`conf`	CoLeCTs: Cooperative Learning Classifier Tables for Resource Management in MPSoCs. ARCS Klajd Zyla, Florian Maurer, Thomas Wild, Andreas Herkersdorf
2023	C	`conf`	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs. VLSI-SoC Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf
2023	A*	`conf`	HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification. DAC Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Clara Kowalsky, Thomas Wild, Andreas Herkersdorf
2023	—	`conf`	LCT-DER: Learning Classifier Table with Dynamic-Sized Experience Replay for Run-time SoC Performance-Power Optimization. GECCO Companion Anmol Surhonne, Florian Maurer, Thomas Wild, Andreas Herkersdorf
2023	—	`conf`	LCT-TL : Learning Classifier Table (LCT) with Transfer Learning for runtime SoC performance-power optimization. MCSoC Anmol Surhonne, Florian Maurer, Thomas Wild, Andreas Herkersdorf
2023	C	`conf`	Priority-aware Inter-Server Receive Side Scaling. PDP Franz Biersack, Kilian Holzinger, Henning Stubbe, Thomas Wild, Georg Carle, Andreas Herkersdorf
2023	—	`conf`	X-MAPE: Extending 6G-Connected Self-Adaptive Systems with Reflexive Actions. NFV-SDN Marco Liess, Julian Demicoli, Tobias Tiedje, Matthias Lohrmann, Matthias Nickel, M. Luniak, Dimitrios A. Prousalis, Thomas Wild, Ronald Tetzlaff, Diana Göhringer, Christian Mayr, Karlheinz Bock, Sebastian Steinhorst, Andreas Herkersdorf
2022	J	`jnl`	Fine-Grained Power Modeling of Multicore Processors Using FFNNs. Int. J. Parallel Program. Mark Sagi, Nguyen Anh Vu Doan, Nael Fasfous, Thomas Wild, Andreas Herkersdorf
2022	—	`conf`	GAE-LCT: A Run-Time GA-Based Classifier Evolution Method for Hardware LCT Controlled SoC Performance-Power Optimization. ARCS Anmol Surhonne, Nguyen Anh Vu Doan, Florian Maurer, Thomas Wild, Andreas Herkersdorf
2022	—	`conf`	GLS Tracing: Gem5-based Low-intrusive Software Tracing. NorCAS Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf
2022	B	`conf`	SmartNIC-based Load Management and Network Health Monitoring for Time Sensitive Applications. NOMS Kilian Holzinger, Franz Biersack, Henning Stubbe, Angela Gonzalez Mariño, Abdoul Kane, Francesc Fons, Haigang Zhang, Thomas Wild, Andreas Herkersdorf, Georg Carle
2022	J	`jnl`	rmap: An R package to plot and compare tabular data on customizable maps across scenarios and time. J. Open Source Softw. Zarrar Khan, Mengqi Zhao, Chris R. Vernon, Thomas Wild, Brinda Yarlagadda
2021	J	`jnl`	DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures. Int. J. Parallel Program. Sven Rheindt, Sebastian Maier, Nora Pohle, Lars Nolte, Oliver Lenke, Florian Schmaus, Thomas Wild, Wolfgang Schröder-Preikschat, Andreas Herkersdorf
2021	J	`jnl`	DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures. Int. J. Parallel Program. Akshay Srivatsa, Mostafa Mansour, Sven Rheindt, Dirk Gabriel, Thomas Wild, Andreas Herkersdorf
2021	J	`jnl`	Exploring a Hybrid Voting-based Eviction Policy for Caches and Sparse Directories on Manycore Architectures. Microprocess. Microsystems Akshay Srivatsa, Nael Fasfous, Nguyen Anh Vu Doan, Sebastian Nagel, Thomas Wild, Andreas Herkersdorf
2021	A	`conf`	Long Short-Term Memory Neural Network-based Power Forecasting of Multi-Core Processors. DATE Mark Sagi, Martin Rapp, Heba Khdr, Yizhe Zhang, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Jörg Henkel, Andreas Herkersdorf
2021	—	`conf`	PEPERONI: Pre-Estimating the Performance of Near-Memory Integration. MEMSYS Oliver Lenke, Richard Petri, Thomas Wild, Andreas Herkersdorf
2021	A	`conf`	Precise real-time monitoring of time-critical flows. CoNEXT Kilian Holzinger, Henning Stubbe, Franz Biersack, Angela Gonzalez Mariño, Abdoul Kane, Francisco Fons Lluis, Haigang Zhang, Thomas Wild, Andreas Herkersdorf, Georg Carle
2021	J	`jnl`	Protection switching schemes and mapping strategies for fail-operational hard real-time NoCs. Microprocess. Microsystems Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf
2021	J	`jnl`	plutus: An R package to calculate electricity investments and stranded assets from the Global Change Analysis Model (GCAM). J. Open Source Softw. Mengqi Zhao, Matthew Binsted, Thomas Wild, Zarrar Khan, Brinda Yarlagadda, Gokul Iyer, Chris R. Vernon, Pralit Patel, Sílvia da Silva, Katherine V. Calvin
2020	J	`jnl`	A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mark Sagi, Nguyen Anh Vu Doan, Martin Rapp, Thomas Wild, Jörg Henkel, Andreas Herkersdorf
2020	—	`conf`	Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs. NorCAS Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf
2020	—	`conf`	Fine-Grained Power Modeling of Multicore Processors Using FFNNs. SAMOS Mark Sagi, Nguyen Anh Vu Doan, Nael Fasfous, Thomas Wild, Andreas Herkersdorf
2020	—	`conf`	HyVE: A Hybrid Voting-based Eviction Policy for Caches. NorCAS Akshay Srivatsa, Sebastian Nagel, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf
2020	C	`conf`	Inter-Server RSS: Extending Receive Side Scaling for Inter-Server Workload Distribution. PDP Andreas Oeldemann, Franz Biersack, Thomas Wild, Andreas Herkersdorf
2020	J	`jnl`	Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs. ACM Trans. Design Autom. Electr. Syst. Yong Hu, Marcel Mettler, Daniel Mueller-Gritschneder, Thomas Wild, Andreas Herkersdorf, Ulf Schlichtmann
2020	—	`conf`	On-Chip Democracy: A Study on the Use of Voting Systems for Computer Cache Memory Management. IEEM Nguyen Anh Vu Doan, Akshay Srivatsa, Nael Fasfous, Sebastian Nagel, Thomas Wild, Andreas Herkersdorf
2020	—	`conf`	X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-Based MPSoCs. ARCS Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Temur Sabirov, Tim Twardzik, Thomas Wild, Andreas Herkersdorf
2020	—	`conf`	X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures. MEMSYS Sven Rheindt, Temur Sabirov, Oliver Lenke, Thomas Wild, Andreas Herkersdorf
2019	—	`conf`	A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC. ARCS Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf
2019	—	`conf`	APEC: improved acknowledgement prioritization through erasure coding in bufferless NoCs. NOCS Michael Vonbun, Adrian Schiechel, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf
2019	—	`conf`	Channel mapping strategies for effective protection switching in fail-operational hard real-time NoCs. NOCS Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf
2019	—	`conf`	CoD: Coherence-on-Demand - Runtime Adaptable Working Set Coherence for DSM-Based Manycore Architectures. SAMOS Akshay Srivatsa, Sven Rheindt, Dirk Gabriel, Thomas Wild, Andreas Herkersdorf
2019	—	`conf`	Cryptographic Hashing in P4 Data Planes. ANCS Dominik Scholz, Andreas Oeldemann, Fabien Geyer, Sebastian Gallenmüller, Henning Stubbe, Thomas Wild, Andreas Herkersdorf, Georg Carle
2019	—	`conf`	Multi-Objective Optimization of Channel Mapping for Fail-Operational Hybrid TDM NoCs. CANDAR Workshops Nguyen Anh Vu Doan, Max Koenen, Thomas Wild, Andreas Herkersdorf
2019	—	`conf`	Multicore Power Estimation using Independent Component Analysis Based Modeling. MCSoC Mark Sagi, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf
2019	—	`conf`	NEMESYS: near-memory graph copy enhanced system-software. MEMSYS Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf
2019	—	`conf`	Network Coding in Networks-on-Chip with Lossy Links. ARCS Michael Vonbun, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf
2019	—	`conf`	Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications. SoCC Thomas Goldbrunner, Nguyen Anh Vu Doan, Diogo Poças, Thomas Wild, Andreas Herkersdorf
2019	—	`conf`	SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore Architectures. SAMOS Sven Rheindt, Sebastian Maier, Florian Schmaus, Thomas Wild, Wolfgang Schröder-Preikschat, Andreas Herkersdorf
2019	Misc	`conf`	The information processing factory: a paradigm for life cycle management of dependable systems. CODES+ISSS Eberle A. Rambo, Thawra Kadeed, Rolf Ernst, Minjun Seo, Fadi J. Kurdahi, Bryan Donyanavard, Caio Batista de Melo, Biswadip Maity, Kasra Moazzemi, Kenneth Michael Stewart, Saehanseul Yi, Amir M. Rahmani, Nikil D. Dutt, Florian Maurer, Nguyen Anh Vu Doan, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf
2018	—	`conf`	BiSME: A Hardware Coprocessor to Perform Signature Matching at Multi-Gigabit Rates. ASAP Subramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf, Thomas Wild
2018	—	`conf`	CaCAO: Complex and Compositional Atomic Operations for NoC-Based Manycore Platforms. ARCS Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild, Andreas Herkersdorf
2018	A	`conf`	Design methodologies for enabling self-awareness in autonomous systems. DATE Armin Sadighi, Bryan Donyanavard, Thawra Kadeed, Kasra Moazzemi, Tiago Mück, Ahmed Nassar, Amir M. Rahmani, Thomas Wild, Nikil D. Dutt, Rolf Ernst, Andreas Herkersdorf, Fadi J. Kurdahi
2018	B	`conf`	FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet. FPL Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf
2018	—	`conf`	Memory Access Pattern Profiling for Streaming Applications Based on MATLAB Models. PATMOS Thomas Goldbrunner, Thomas Wild, Andreas Herkersdorf
2018	J	`jnl`	Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS. Proc. IEEE Mischa Möstl, Johannes Schlatow, Rolf Ernst, Nikil D. Dutt, Ahmed Nassar, Amir-Mohammad Rahmani, Fadi J. Kurdahi, Thomas Wild, Armin Sadighi, Andreas Herkersdorf
2017	C	`conf`	A Divide and Conquer State Grouping Method for Bitmap Based Transition Compression. PDCAT Subramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf, Thomas Wild
2017	A	`conf`	A non-intrusive, operating system independent spinlock profiler for embedded multicore systems. DATE Lin Li, Philipp Wagner, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf
2017	C	`conf`	Adaptive Reliability for Fault Tolerant Multicore Systems. DSD Ihsen Alouani, Thomas Wild, Andreas Herkersdorf, Smaïl Niar
2017	J	`jnl`	DiaSys: Improving SoC insight through on-chip diagnosis. J. Syst. Archit. Philipp Wagner, Thomas Wild, Andreas Herkersdorf
2017	J	`jnl`	Efficient task spawning for shared memory and message passing in many-core architectures. J. Syst. Archit. Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jan Heisswolf, Jürgen Becker, Andreas Weichslgartner, Jürgen Teich
2017	—	`conf`	Reducing Data Center Resource Over-Provisioning Through Dynamic Load Management for Virtualized Network Functions. ARCS Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf
2017	—	`conf`	Region based cache coherence for tiled MPSoCs. SoCC Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf
2016	C	`conf`	A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems. SCOPES Lin Li, Philipp Wagner, Ramesh Ramaswamy, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf
2016	J	`jnl`	Dark silicon management: an integrated and coordinated cross-layer approach. it Inf. Technol. Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel
2016	—	`conf`	DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip. ARCS Philipp Wagner, Thomas Wild, Andreas Herkersdorf
2016	—	`conf`	Estimation of End-to-End Packet Error Rates for NoC Multicasts. ARCS Michael Vonbun, Thomas Wild, Andreas Herkersdorf
2016	Misc	`conf`	Hardware acceleration of signature matching through multi-layer transition bit masking. ITNAC Subramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf, Thomas Wild
2016	J	`jnl`	Improving SoC Insight Through On-Chip Diagnosis. CoRR Philipp Wagner, Thomas Wild, Andreas Herkersdorf
2016	J	`jnl`	MPSoC application resilience by hardware-assisted communication virtualization. Microelectron. Reliab. Stefan Rosch, Holm Rauchfuss, Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf
2016	C	`conf`	Resolving Performance Interference in SR-IOV Setups with PCIe Quality-of-Service Extensions. DSD Andre Oliver Richter, Christian Herber, Thomas Wild, Andreas Herkersdorf
2016	C	`conf`	TCU: A Multi-Objective Hardware Thread Mapping Unit for HPC Clusters. ISC Ravi Kumar Pujari, Thomas Wild, Andreas Herkersdorf
2016	—	`conf`	What happens on an MPSoC stays on an MPSoC - unfortunately! ISIC Philipp Wagner, Lin Li, Thomas Wild, Albrecht Mayer, Andreas Herkersdorf
2015	B	`conf`	A Hardware/Software Approach for Mitigating Performance Interference Effects in Virtualized Environments Using SR-IOV. CLOUD Andre Oliver Richter, Christian Herber, Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf
2015	C	`conf`	A hardware-based multi-objective thread mapper for tiled manycore architectures. ICCD Ravi Kumar Pujari, Thomas Wild, Andreas Herkersdorf
2015	J	`jnl`	Adaptive multi-layer techniques for increased system dependability. it Inf. Technol. Lars Bauer, Jörg Henkel, Andreas Herkersdorf, Michael A. Kochte, Johannes Maximilian Kühn, Wolfgang Rosenstiel, Thomas Schweizer, Stefan Wallentowitz, Volker Wenzel, Thomas Wild, Hans-Joachim Wunderlich, Hongyan Zhang
2015	J	`jnl`	Denial-of-Service attacks on PCI passthrough devices: Demonstrating the impact on network- and storage-I/O performance. J. Syst. Archit. Andre Oliver Richter, Christian Herber, Thomas Wild, Andreas Herkersdorf
2015	—	`conf`	Fault-tolerant communication in invasive networks on chip. AHS Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klopfer, Jürgen Teich, Thomas Wild, Andreas Herkersdorf, Jürgen Becker
2015	—	`conf`	Network Interface with Task Spawning Support for NoC-Based DSM Architectures. ARCS Aurang Zaib, Jan Heißwolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf
2015	A	`conf`	Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling. DATE Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf
2015	—	`conf`	Sharer status-based caching in tiled multiprocessor systems-on-chip. SpringSim (HPS) P. Parayil Mana Damodaran, Aurang Zaib, Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf
2014	J	`jnl`	A Layered Modeling and Simulation Approach to investigate Resource-aware Computing in MPSoCs. CoRR Aurang Zaib, Prashanth Raju, Thomas Wild, Andreas Herkersdorf
2014	A	`conf`	A network virtualization approach for performance isolation in controller area network (CAN). RTAS Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf
2014	—	`ed.`	ARCS 2014 - 27th International Conference on Architecture of Computing Systems, Workshop Proceedings, February 25-28, 2014, Luebeck, Germany, University of Luebeck, Institute of Computer Engineering ARCS Workshops Walter Stechele, Thomas Wild
2014	—	`conf`	Deadline-Aware Interrupt Coalescing in Controller Area Network (CAN). HPCC/CSS/ICESS Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf
2014	C	`conf`	Dependable task and communication migration in tiled manycore system-on-chip. FDL Stefan Wallentowitz, Stefan Rosch, Thomas Wild, Andreas Herkersdorf, Volker Wenzel, Jörg Henkel
2014	—	`conf`	Performance Isolation Exposure in Virtualized Platforms with PCI Passthrough I/O Sharing. ARCS Andre Oliver Richter, Christian Herber, Holm Rauchfuss, Thomas Wild, Andreas Herkersdorf
2014	A	`conf`	System integration - The bridge between More than Moore and More Moore. DATE Andy Heinig, Manfred Dietrich, Andreas Herkersdorf, Felix Miller, Thomas Wild, Kai Hahn, Armin Grünewald, Rainer Brück, Steffen Krohnert, Jochen Reisinger
2014	—	`conf`	The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. ARCS Workshops Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker
2013	C	`conf`	AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. DSD Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf
2013	—	`conf`	HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation. ARCS Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf
2013	—	`conf`	Hardware Supported Adaptive Data Collection for Networks on Chip. IPDPS Workshops Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, Thomas Wild, Andreas Herkersdorf, Jürgen Teich, Jürgen Becker
2013	—	`conf`	New Algorithm for Analysis of Off-target Effects in siRNA Screens. BIOINFORMATICS Karol Kozak, Sandra Kaestner, Thomas Wild, Andreas Vonderheit, Benjamin Misselwitz, Ulrike Kutay, Gabor Csucs
2013	J	`jnl`	Open Tiled Manycore System-on-Chip CoRR Stefan Wallentowitz, Philipp Wagner, Michael Tempelmeier, Thomas Wild, Andreas Herkersdorf
2013	—	`conf`	Potentials and Challenges for Multi-Core Processors in Robotic Applications. GI-Jahrestagung Andreas Herkersdorf, Johny Paul, Ravi Kumar Pujari, Walter Stechele, Stefan Wallentowitz, Thomas Wild, Aurang Zaib
2013	J	`jnl`	Virtual networks - distributed communication resource management. ACM Trans. Reconfigurable Technol. Syst. Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker
2013	J	`jnl`	Virtualized and fault-tolerant inter-layer-links for 3D-ICs. Microprocess. Microsystems Felix Miller, Thomas Wild, Andreas Herkersdorf
2012	B	`conf`	A framework for Open Tiled Manycore System-On-Chip. FPL Stefan Wallentowitz, Andreas Lankes, Aurang Zaib, Thomas Wild, Andreas Herkersdorf
2012	C	`conf`	An integrated simulation framework for invasive computing. FDL Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild, Aurang Zaib
2012	J	`jnl`	Benefits of selective packet discard in networks-on-chip. ACM Trans. Archit. Code Optim. Andreas Lankes, Thomas Wild, Stefan Wallentowitz, Andreas Herkersdorf
2012	—	`conf`	Enhanced Reliability in Tiled Manycore Architectures through Transparent Task Relocation. ARCS Workshops Holm Rauchfuss, Thomas Wild, Andreas Herkersdorf
2012	—	`conf`	Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. IPDPS Workshops Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker
2012	—	`conf`	Invasive manycore architectures. ASP-DAC Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe
2012	J	`jnl`	Multicore Enablement for Automotive Cyber Physical Systems. it Inf. Technol. Andreas Herkersdorf, Hans-Ulrich Michel, Holm Rauchfuss, Thomas Wild
2012	—	`conf`	System-level software performance simulation considering out-of-order processor execution. ISSoC Roman Plyaskin, Thomas Wild, Andreas Herkersdorf
2012	C	`conf`	TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs. DSD Felix Miller, Thomas Wild, Andreas Herkersdorf
2011	—	`conf`	Accelerating collective communication in message passing on manycore System-on-Chip. ICSAMOS Stefan Wallentowitz, Marcel Meyer, Thomas Wild, Andreas Herkersdorf
2011	J	`jnl`	Advanced Packet Segmentation and Buffering Algorithms in Network Processors. Trans. High Perform. Embed. Archit. Compil. Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf
2011	—	`ch.`	Hardware Support for Efficient Resource Utilization in Manycore Processor Systems. Multiprocessor System-on-Chip Andreas Herkersdorf, Andreas Lankes, Michael Meitinger, Rainer Ohlendorf, Stefan Wallentowitz, Thomas Wild, Johannes Zeppenfeld
2010	—	`conf`	A folded pipeline network processor architecture for 100 Gbit/s networks. ANCS Kimon Karras, Thomas Wild, Andreas Herkersdorf
2010	—	`conf`	An Application-Aware Load Balancing Strategy for Network Processors. HiPEAC Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf
2010	—	`conf`	Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. NOCS Andreas Lankes, Thomas Wild, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig
2010	—	`ch.`	FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors. Dynamically Reconfigurable Systems Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf
2009	C	`conf`	Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources. DSD Andreas Lankes, Thomas Wild, Andreas Herkersdorf
2008	—	`conf`	A Hardware Packet Re-Sequencer Unit for Network Processors. ARCS Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf
2008	J	`jnl`	A Processing Path Dispatcher in Network Processor MPSoCs. IEEE Trans. Very Large Scale Integr. Syst. Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf
2008	—	`conf`	Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design. ISVLSI Zhonglei Wang, Thomas Wild, Stefan Rüping, Bernhard Lippmann
2008	—	`conf`	Buffer allocation for advanced packet segmentation in Network Processors. ASAP Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf
2008	—	`conf`	FlexPath NP - A network processor architecture with flexible processing paths. SoC Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf
2008	—	`conf`	Improving memory subsystem performance in network processors with smart packet segmentation. ICSAMOS Kimon Karras, Daniel Llorente, Thomas Wild, Andreas Herkersdorf
2008	B	`conf`	Network processors. FPL Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf
2008	—	`conf`	System Level Simulation of Autonomic SoCs with TAPES. ARCS Andreas Lankes, Thomas Wild, Johannes Zeppenfeld
2007	—	`conf`	A Programmable Stream Processing Engine for Packet Manipulation in Network Processors. ISVLSI Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf
2007	C	`conf`	Power Estimation of Time Variant SoCs with TAPES. DSD Andreas Lankes, Thomas Wild, Johannes Zeppenfeld
2007	J	`jnl`	Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications. J. Syst. Archit. Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf
2006	—	`conf`	Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. ICSAMOS Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf
2006	A	`conf`	Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. DATE Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
2006	J	`jnl`	Queuing algorithm for speculative Network Processors. Int. J. High Perform. Comput. Netw. Jürgen Foag, Thomas Wild
2006	—	`conf`	Reconfigurable Processing Units vs. Reconfigurable Interconnects. Dynamically Reconfigurable Architectures Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, Thomas Wild
2005	Misc	`conf`	FlexPath NP: a network processor concept with application-driven flexible processing paths. CODES+ISSS Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild
2005	—	`conf`	Predictive processing architecture extension for network processors. ICECS Jürgen Foag, Thomas Wild
2005	J	`jnl`	TAPES - Trace-based architecture performance evaluation with SystemC. Des. Autom. Embed. Syst. Thomas Wild, Andreas Herkersdorf, Gyoo-Yeong Lee
2004	—	`conf`	Queuing Algorithm for Speculative Network Processors. HPCS Jürgen Foag, Thomas Wild
2003	C	`conf`	A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. DSD Winthir Brunnbauer, Thomas Wild, Jürgen Foag, Nuria Pazos
2003	—	`—`	Ein rekursives Verfahren zur Abbildung und zum Scheduling von Prozess-Graphen mit Kontrollabhängigkeiten. Thomas Wild
2003	Misc	`conf`	Mapping and Scheduling for Architecture Exploration of Networking SoCs. VLSI Design Thomas Wild, Jürgen Foag, Nuria Pazos, Winthir Brunnbauer
2002	C	`conf`	Predictive methodology for high-performance networking. ISCC Jürgen Foag, Thomas Wild, Nuria Pazos, Winthir Brunnbauer
2002	—	`conf`	Self-Adaptive Parallel Processing Architecture For High-speed Networking. HPCS Jürgen Foag, Nuria Pazos, Thomas Wild, Winthir Brunnbauer