Thomas W. Williams

66 papers A* 4A 20B 1C 3Misc 6Journal 19Unranked 13

Year	Rank	Type	Title / Venue / Authors
2008	—	`conf`	EDA to the Rescue of the Silicon Roadmap. ISMVL Thomas W. Williams
2008	—	`conf`	Evaluation of Entropy Driven Compression Bounds on Industrial Designs. ATS Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams
2008	J	`jnl`	Historical Perspective on Scan Compression. IEEE Des. Test Comput. Rohit Kapur, Subhasish Mitra, Thomas W. Williams
2008	—	`conf`	Reaching the limits of low power design. ASP-DAC J. S. Hobbs, Thomas W. Williams
2008	B	`conf`	The Future Is Low Power and Test. ETS Thomas W. Williams
2007	C	`conf`	Accurately Determining Bridging Defects from Layout. DDECS Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams
2007	J	`jnl`	DFT MAX and Power. J. Low Power Electron. Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri
2007	—	`conf`	EDA to the Rescue of the Silicon Roadmap. ISQED Thomas W. Williams
2007	A	`conf`	Fundamentals of timing information for test: How simple can we get? ITC Rohit Kapur, Jindrich Zejda, Thomas W. Williams
2007	Misc	`conf`	Minimizing the Impact of Scan Compression. VTS Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
2005	—	`conf`	Design for Testability: The Path to Deep Submicron. Asian Test Symposium Thomas W. Williams
2005	A	`conf`	Efficient compression of deterministic patterns into multiple PRPG seeds. ITC Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur
2005	J	`jnl`	TTTC recognizes test visionary's lifetime contribution. IEEE Des. Test Comput. Thomas W. Williams
2004	Misc	`conf`	Changing the Scan Enable during Shift. VTS Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams
2003	Misc	`conf`	A Reconfigurable Shared Scan-in Architecture. VTS Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams
2003	A	`conf`	Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. DATE Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch
2003	A	`conf`	Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
2002	A	`conf`	Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
2002	A	`conf`	Directed-Binary Search in Logic BIST Diagnostics. DATE Rohit Kapur, Thomas W. Williams, M. Ray Mercer
2002	J	`jnl`	Dynamic Scan: Driving Down the Cost of Test. Computer Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams
2002	A*	`conf`	Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
2002	A	`conf`	Fast seed computation for reseeding shift register in test pattern compression. ICCAD Nahmsuk Oh, Rohit Kapur, Thomas W. Williams
2002	—	`conf`	Manufacturing Test of SoCs. Asian Test Symposium Rohit Kapur, Thomas W. Williams
2001	A	`conf`	A new methodology for improved tester utilization. ITC Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir
2001	A	`conf`	Design of compactors for signature-analyzers in built-in self-test. ITC Peter Wohl, John A. Waicukauski, Thomas W. Williams
2001	J	`jnl`	Strategies for Low-Cost Test. IEEE Des. Test Comput. Rohit Kapur, R. Chandramouli, Thomas W. Williams
2001	A	`conf`	Tester retargetable patterns. ITC Rohit Kapur, Thomas W. Williams
2000	J	`jnl`	An industrial view of electronic design automation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Don MacMillen, Raul Camposano, Dwight D. Hill, Thomas W. Williams
2000	—	`conf`	DFT closure. Asian Test Symposium Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu
2000	—	`conf`	Design for Testability in Nanometer Technologies; Searching for Quality. ISQED Thomas W. Williams, Rohit Kapur
2000	Misc	`conf`	How Should Fault Coverage Be Defined? VTS Thomas W. Williams, Stephen K. Sunter
2000	J	`jnl`	The Mutating Metric for Benchmarking Test. IEEE Des. Test Comput. Rohit Kapur, Cy Hay, Thomas W. Williams
1999	J	`jnl`	IEEE-USA and the Issue of Member Choice. Computer Thomas W. Williams
1999	A	`conf`	Testing in Nanometer Technologies. DATE Thomas W. Williams
1999	J	`jnl`	Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction. Computer Rohit Kapur, Thomas W. Williams
1998	—	`conf`	The New Frontier for Testing: Nano Meter Technologies. Asian Test Symposium Thomas W. Williams
1996	C	`conf`	A Better ATPG Algorithm and Its Design Principles. ICCD Li-C. Wang, M. Ray Mercer, Thomas W. Williams
1996	J	`jnl`	A weighted random pattern test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
1996	J	`jnl`	Defect level evaluation in an IC design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams
1996	A	`conf`	I ITC Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
1996	—	`conf`	Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly
1996	A	`conf`	Using Target Faults To Detect Non-Tartget Defects. ITC Li-C. Wang, M. Ray Mercer, Thomas W. Williams
1995	—	`conf`	Enhanced testing performance via unbiased test sets. ED&TC Li-C. Wang, M. Ray Mercer, Thomas W. Williams
1995	A	`conf`	On Efficiently and Reliably Achieving Low Defective Part Levels. ITC Li-C. Wang, M. Ray Mercer, Thomas W. Williams
1995	Misc	`conf`	On the decline of testing efficiency as fault coverage approaches 100%. VTS Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams
1994	A	`conf`	Design of an Efficient Weighted-Random-Pattern Generation System. ITC Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
1994	—	`conf`	Fault Modeling and Defect Level Projections in Digital ICs. EDAC-ETC-EUROASIC José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams
1994	Misc	`conf`	Limitations in predicting defect level based on stuck-at fault coverage. VTS Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams
1993	C	`conf`	Design for Testability: Today and in the Future. ICCD Thomas W. Williams
1992	J	`jnl`	The Total Delay Fault Model and Statistical Delay Fault Coverage. IEEE Trans. Computers Eun Sei Park, M. Ray Mercer, Thomas W. Williams
1991	A	`conf`	Delay Testing Quality in Timing-Optimized Designs. ITC Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer
1991	A	`conf`	Enhancing Board Functional Self-Test by Concurrent Sampling. ITC Kenneth D. Wagner, Thomas W. Williams
1991	A*	`conf`	The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. DAC Thomas W. Williams, Bill Underwood, M. Ray Mercer
1989	J	`jnl`	A statistical model for delay-fault testing. IEEE Des. Test Eun Sei Park, M. Ray Mercer, Thomas W. Williams
1989	—	`conf`	Future Trends in the Testing. IFIP Congress Thomas W. Williams
1988	A	`conf`	Design for Testability of Mixed Signal Integrated Circuits. ITC Kenneth D. Wagner, Thomas W. Williams
1988	A	`conf`	Statistical Delay Fault Coverage and Defect Level for Delay Faults. ITC Eun Sei Park, Thomas W. Williams, M. Ray Mercer
1986	J	`jnl`	Design of testable logic circuits. Proc. IEEE Thomas W. Williams
1985	J	`jnl`	Test Length in a Self-Testing Environment. IEEE Des. Test Thomas W. Williams
1984	J	`jnl`	VLSI Testing. Computer Thomas W. Williams
1982	A	`conf`	Analysis of the Switching Behavior of Combinatorial Logic Networks. ITC Eugen I. Muehldorf, Thomas W. Williams
1982	J	`jnl`	Design for Testability - A Survey. IEEE Trans. Computers Thomas W. Williams, Kenneth P. Parker
1982	A*	`conf`	Design for testability. DAC Thomas W. Williams
1979	J	`jnl`	Testing Logic Networks and Designing for Testability. Computer Thomas W. Williams, Kenneth P. Parker
1977	A*	`conf`	A logic design structure for LSI testability. DAC Edward B. Eichelberger, Thomas W. Williams
1972	J	`jnl`	Effect of Record Length on Noise-Induced Error in the Cross Correlation Estimate. IEEE Trans. Syst. Man Cybern. Daniel J. Krause, John W. Steadman, Thomas W. Williams