Thomas R. Shiple

25 papers A* 10A 6B 3C 1Journal 3Unranked 2
YearRankTypeTitle / Venue / Authors
2012 J jnl
Constructive Boolean circuits and the exactness of timed ternary simulation.
Formal Methods Syst. Des.
Michael Mendler, Thomas R. Shiple, Gérard Berry
2011 — conf
Multi-mode redundancy removal.
ISQED
Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho
2002 A conf
Combinational equivalence checking through function transformation.
ICCAD
Hee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple
2002 J jnl
Formula-Dependent Equivalence for Compositional CTL Model Checking.
Formal Methods Syst. Des.
Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2002 B conf
Simplifying Circuits for Formal Verification Using Parametric Representation.
FMCAD
In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley
2001 J jnl
Efficient control state-space search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Adnan Aziz, James H. Kukula, Thomas R. Shiple, Jun Yuan
2001 A conf
Non-linear Quantification Scheduling in Image Computation.
ICCAD
Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Thomas R. Shiple, Helmut Veith, Dong Wang
2000 A* conf
Building Circuits from Relations.
CAV
James H. Kukula, Thomas R. Shiple
2000 A conf
Smart Simulation Using Collaborative Formal and Simulation Engines.
ICCAD
Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long
1999 A conf
Least fixpoint approximations for reachability analysis.
ICCAD
In-Ho Moon, James H. Kukula, Thomas R. Shiple, Fabio Somenzi
1998 A* conf
A Comparison of Presburger Engines for EFSM Reachability.
CAV
Thomas R. Shiple, James H. Kukula, Rajeev K. Ranjan
1998 A* conf
Approximation and Decomposition of Binary Decision Diagrams.
DAC
Kavita Ravi, Kenneth L. McMillan, Thomas R. Shiple, Fabio Somenzi
1998 A* conf
Hybrid Verification Using Saturated Simulation.
DAC
Adnan Aziz, James H. Kukula, Thomas R. Shiple
1998 B conf
Techniques for Implicit State Enumeration of EFSMs.
FMCAD
James H. Kukula, Thomas R. Shiple, Adnan Aziz
1996 — conf
Constructive Analysis of Cyclic Circuits.
ED&TC
Thomas R. Shiple, Gérard Berry, Hervé J. Touati
1996 B conf
VIS.
FMCAD
Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
1996 A* conf
VIS: A System for Verification and Synthesis.
CAV
Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
1994 A* conf
Formula-Dependent Equivalence for Compositional CTL Model Checking.
CAV
Adnan Aziz, Thomas R. Shiple, Vigyan Singhal
1994 A* conf
HSIS: A BDD-Based Environment for Formal Verification.
DAC
Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994 A* conf
Heuristic Minimization of BDDs Using Don't Cares.
DAC
Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
1994 C conf
Two-phase Logic Design by Hardware Flowcharts.
ICCD
Kevin Covey, Sandra Murdock, Thomas R. Shiple
1993 A* conf
A Unified Approach to Language Containment and Fair CTL Model Checking.
DAC
Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan
1992 A* conf
Automatic Reduction in CTL Compositional Model Checking.
CAV
Thomas R. Shiple, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
1992 A conf
Automatic compositional minimization in CTL model checking.
ICCAD
Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
1989 A conf
CLEO: a CMOS layout generator.
ICCAD
Antun Domic, Samuel Levitin, Nathan Phillips, Channeary Thai, Thomas R. Shiple, Dilip Bhavsar, Clint Bissel