Thomas Polzer

23 papers C 10Journal 6Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
Tragbare Multisensormodule zur sensorgestützten Erfassung von Parametern bei Einsatzübungen.
Elektrotech. Informationstechnik
Stefan Paschek, Thomas Kuschel, Parisay Alibazibehbahani, Martin Stohanzl, Benjamin Aigner, Thomas Polzer, Wilfried Kubinger
2023 C conf
Automated Evaluation System for Microcontroller Assignments.
EDUCON
Fabian Steiner, Bernhard Lueger, Bernhard Wallisch, Thomas Polzer
2019 J jnl
An Experimental Study of Metastability-Induced Glitching Behavior.
J. Circuits Syst. Comput.
Thomas Polzer, Florian Huemer, Andreas Steininger
2018 J jnl
Refined metastability characterization using a time-to-digital converter.
Microelectron. Reliab.
Thomas Polzer, Florian Huemer, Andreas Steininger
2018 C conf
Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA.
DDECS
Florian Huemer, Thomas Polzer, Andreas Steininger
2017 J jnl
A Model for the Metastability Delay of Sequential Elements.
J. Circuits Syst. Comput.
Thomas Polzer, Andreas Steininger
2017 — conf
Measuring Metastability with Free-Running Clocks.
ASYNC
Robert Najvirt, Thomas Polzer, Andreas Steininger
2017 C conf
Measuring metastability using a time-to-digital converter.
DDECS
Thomas Polzer, Florian Huemer, Andreas Steininger
2017 — conf
Metastability-Aware Memory-Efficient Time-to-Digital Converters.
ASYNC
Matthias Függer, Attila Kinali, Christoph Lenzen, Thomas Polzer
2016 C conf
A general approach for comparing metastable behavior of digital CMOS gates.
DDECS
Thomas Polzer, Andreas Steininger
2016 J jnl
On the Appropriate Handling of Metastable Voltages in FPGAs.
J. Circuits Syst. Comput.
Thomas Polzer, Robert Najvirt, Florian Beck, Andreas Steininger
2015 C conf
Containment of Metastable Voltages in FPGAs.
DDECS
Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger
2015 C conf
Enhanced Metastability Characterization Based on AC Analysis.
DSD
Thomas Polzer, Andreas Steininger
2015 C conf
Measuring the Distribution of Metastable Upsets over Time.
DSD
Thomas Polzer, Andreas Steininger
2013 — conf
An Approach for Efficient Metastability Characterization of FPGAs through the Designer.
ASYNC
Thomas Polzer, Andreas Steininger
2013 J jnl
An infrastructure for accurate characterization of single-event transients in digital circuits.
Microprocess. Microsystems
Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger, Michael Hofbauer, Kurt Schweiger, Horst Dietrich, Kerstin Schneider-Hornstein, Horst Zimmermann, Kay-Obbe Voss, Bruno Merk, Michael Hajek
2013 C conf
Digital Late-Transition Metastability Simulation Model.
DSD
Thomas Polzer, Andreas Steininger
2013 — conf
Metastability characterization for muller C-elements.
PATMOS
Thomas Polzer, Andreas Steininger
2013 — conf
SET propagation in micropipelines.
PATMOS
Thomas Polzer, Andreas Steininger
2012 — conf
A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding.
ACSD
Jakob Lechner, Martin Lampacher, Thomas Polzer
2012 C conf
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip.
DSD
Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid
2012 — conf
Muller C-Element Metastability Containment.
PATMOS
Thomas Polzer, Andreas Steininger, Jakob Lechner
2009 C conf
A Metastability-Free Multi-synchronous Communication Scheme for SoCs.
SSS
Thomas Polzer, Thomas Handl, Andreas Steininger