Thomas M. Conte

127 papers A* 17A 6B 4C 6Misc 4Journal 53Unranked 31

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Blueprint for Q-CS1, an Introductory Quantum Programming Course. SIGCSE (2) Austin J. Adams, Rodrigo Borela, Jeffrey S. Young, Thomas M. Conte
2025	A	`conf`	ASDF: A Compiler for Qwerty, a Basis-Oriented Quantum Programming Language. CGO Austin J. Adams, Sharjeel Khan, Arjun S. Bhamra, Ryan R. Abusaada, Anthony M. Cabrera, Cameron C. Hoechst, Travis S. Humble, Jeffrey S. Young, Thomas M. Conte
2025	J	`jnl`	ASDF: A Compiler for Qwerty, a Basis-Oriented Quantum Programming Language. CoRR Austin J. Adams, Sharjeel Khan, Arjun S. Bhamra, Ryan R. Abusaada, Anthony M. Cabrera, Cameron C. Hoechst, Travis S. Humble, Jeffrey S. Young, Thomas M. Conte
2025	—	`conf`	RASSM: Residue-based Acceleration of Single Sparse Matrix Computation via Adaptive Tiling. ASPLOS (1) Anirudh Jain, Pulkit Gupta, Thomas M. Conte
2024	J	`jnl`	Qwerty: A Basis-Oriented Quantum Programming Language. CoRR Austin J. Adams, Sharjeel Khan, Jeffrey S. Young, Thomas M. Conte
2023	—	`conf`	Enabling Multi-threading in Heterogeneous Quantum-Classical Programming Models. IPDPS Workshops Akihiro Hayashi, Austin J. Adams, Jeffrey Young, Alexander J. McCaskey, Eugene F. Dumitrescu, Vivek Sarkar, Thomas M. Conte
2023	J	`jnl`	Enabling Multi-threading in Heterogeneous Quantum-Classical Programming Models. CoRR Akihiro Hayashi, Austin J. Adams, Jeffrey Young, Alexander J. McCaskey, Eugene F. Dumitrescu, Vivek Sarkar, Thomas M. Conte
2023	—	`conf`	Status Update on the IEEE Rebooting Computing Initiative. JVA Thomas M. Conte
2023	—	`conf`	The Invention of Electronic Digital Computing - Plenary Panel Summary. JVA John Vincent Atanasoff, Gordon Bell, Kiril L. Boyanov, Charles G. Call, Carl K. Chang, Thomas M. Conte, Vladimir Getov, John L. Gustafson, Hironori Kasahara, Dejan S. Milojicic, Michael R. Williams
2022	A	`conf`	"Smarter" NICs for faster molecular dynamics: a case study. IPDPS Sara Karamati, Clayton Hughes, K. Scott Hemmert, Ryan E. Grant, Whit Schonbein, Scott Levy, Thomas M. Conte, Jeffrey Young, Richard W. Vuduc
2022	J	`jnl`	"Smarter" NICs for faster molecular dynamics: a case study. CoRR Sara Karamati, Clayton Hughes, K. Scott Hemmert, Ryan E. Grant, Whit Schonbein, Scott Levy, Thomas M. Conte, Jeffrey Young, Richard W. Vuduc
2022	J	`jnl`	Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems. IEEE Trans. Computers Bobin Deng, Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
2021	J	`jnl`	A vision to compute like nature: thermodynamically. Commun. ACM Todd Hylton, Thomas M. Conte, Mark D. Hill
2021	J	`jnl`	Advancing Computing's Foundation of US Industry & Society. CoRR Thomas M. Conte, Ian T. Foster, William Gropp, Mark D. Hill
2021	—	`conf`	Enabling a Programming Environment for an Experimental Ion Trap Quantum Testbed. ICRC Austin J. Adams, Elton Pinto, Jeffrey Young, Creston D. Herold, Alexander J. McCaskey, Eugene F. Dumitrescu, Thomas M. Conte
2021	J	`jnl`	SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads. ACM Trans. Archit. Code Optim. Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook
2020	—	`conf`	Intrepydd: performance, productivity, and portability for data science application kernels. Onward! Tong Zhou, Jun Shirako, Anirudh Jain, Sriseshan Srikanth, Thomas M. Conte, Richard W. Vuduc, Vivek Sarkar
2020	J	`jnl`	MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams. ACM Trans. Archit. Code Optim. Sriseshan Srikanth, Anirudh Jain, Joseph M. Lennon, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
2020	J	`jnl`	Programming Strategies for Irregular Algorithms on the Emu Chick. ACM Trans. Parallel Comput. Eric R. Hein, Srinivas Eswar, Abdurrahman Yasar, Jiajia Li, Jeffrey S. Young, Thomas M. Conte, Ümit V. Çatalyürek, Richard W. Vuduc, E. Jason Riedy, Bora Uçar
2020	C	`conf`	Special Session: Exploring the Ultimate Limits of Adiabatic Circuits. ICCD Michael P. Frank, Robert W. Brocato, Thomas M. Conte, Alexander H. Hsia, Anirudh Jain, Nancy A. Missert, Karpur Shukla, Brian D. Tierney
2019	—	`conf`	Application Performance of Physical System Simulations. PARCO Vladimir Getov, Peter M. Kogge, Thomas M. Conte
2019	—	`conf`	Experimental Insights from the Rogues Gallery. ICRC Jeffrey S. Young, E. Jason Riedy, Thomas M. Conte, Vivek Sarkar, Prasanth Chatarasi, Sriseshan Srikanth
2019	J	`jnl`	Programming Strategies for Irregular Algorithms on the Emu Chick. CoRR Eric R. Hein, Srinivas Eswar, Abdurrahman Yasar, Jiajia Li, Jeffrey S. Young, Thomas M. Conte, Ümit V. Çatalyürek, Rich Vuduc, E. Jason Riedy, Bora Uçar
2019	—	`conf`	Wrangling Rogues: A Case Study on Managing Experimental Post-Moore Architectures. PEARC Will Powell, E. Jason Riedy, Jeffrey S. Young, Thomas M. Conte
2018	—	`ed.`	2018 IEEE 42nd Annual Computer Software and Applications Conference, COMPSAC 2018, Tokyo, Japan, 23-27 July 2018, Volume 1 COMPSAC (1) Sorel Reisman, Sheikh Iqbal Ahamed, Claudio Demartini, Thomas M. Conte, Ling Liu, William R. Claycomb, Motonori Nakamura, Edmundo Tovar, Stelvio Cimato, Chung-Horng Lung, Hiroki Takakura, Ji-Jiang Yang, Toyokazu Akiyama, Zhiyong Zhang, Md. Kamrul Hasan
2018	—	`ed.`	2018 IEEE 42nd Annual Computer Software and Applications Conference, COMPSAC 2018, Tokyo, Japan, 23-27 July 2018, Volume 2 COMPSAC (2) Sorel Reisman, Sheikh Iqbal Ahamed, Claudio Demartini, Thomas M. Conte, Ling Liu, William R. Claycomb, Motonori Nakamura, Edmundo Tovar, Stelvio Cimato, Chung-Horng Lung, Hiroki Takakura, Ji-Jiang Yang, Toyokazu Akiyama, Zhiyong Zhang, Md. Kamrul Hasan
2018	J	`jnl`	Extending Moore's Law via Computationally Error-Tolerant Computing. ACM Trans. Archit. Code Optim. Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank
2018	J	`jnl`	Iterative Modulo Scheduling. IEEE Micro Onur Mutlu, Scott A. Mahlke, Thomas M. Conte, Wen-mei W. Hwu
2018	A*	`conf`	Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank
2018	J	`jnl`	Rebooting Computers to Avoid Meltdown and Spectre. Computer Thomas M. Conte, Erik P. DeBenedictis, Avi Mendelson, Dejan S. Milojicic
2018	J	`jnl`	Standards: Roadmapping Computer Technology Trends Enlightens Industry. Computer F. D. Wright, Thomas M. Conte
2018	—	`conf`	Tackling memory access latency through DRAM row management. MEMSYS Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang
2017	—	`ed.`	41st IEEE Annual Computer Software and Applications Conference, COMPSAC 2017, Turin, Italy, July 4-8, 2017. Volume 1 COMPSAC (1) Sorel Reisman, Sheikh Iqbal Ahamed, Claudio Demartini, Thomas M. Conte, Ling Liu, William R. Claycomb, Motonori Nakamura, Edmundo Tovar, Stelvio Cimato, Chung-Horng Lung, Hiroki Takakura, Ji-Jiang Yang, Toyokazu Akiyama, Zhiyong Zhang, Md. Kamrul Hasan
2017	—	`ed.`	41st IEEE Annual Computer Software and Applications Conference, COMPSAC 2017, Turin, Italy, July 4-8, 2017. Volume 2 COMPSAC (2) Sorel Reisman, Sheikh Iqbal Ahamed, Claudio Demartini, Thomas M. Conte, Ling Liu, William R. Claycomb, Motonori Nakamura, Edmundo Tovar, Stelvio Cimato, Chung-Horng Lung, Hiroki Takakura, Ji-Jiang Yang, Toyokazu Akiyama, Zhiyong Zhang, Md. Kamrul Hasan
2017	J	`jnl`	Architectures for the Post-Moore Era. IEEE Micro Jeffrey S. Vetter, Erik P. DeBenedictis, Thomas M. Conte
2017	J	`jnl`	Challenges to Keeping the Computer Industry Centered in the US. CoRR Thomas M. Conte, Erik P. DeBenedictis, R. Stanley Williams, Mark D. Hill
2017	J	`jnl`	Rebooting Computing: The Road Ahead. Computer Thomas M. Conte, Erik P. DeBenedictis, Paolo A. Gargini, Elie K. Track
2017	—	`conf`	Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C. HPEC Erik P. DeBenedictis, Jeanine E. Cook, Sriseshan Srikanth, Thomas M. Conte
2017	J	`jnl`	Sustaining Moore's Law with 3D Chips. Computer Erik P. DeBenedictis, Mustafa Badaroglu, An Chen, Thomas M. Conte, Paolo A. Gargini
2017	—	`conf`	The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing. ICRC Sriseshan Srikanth, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook
2016	J	`jnl`	A Brief Survey of Non-Residue Based Computational Error Correction. CoRR Sriseshan Srikanth, Bobin Deng, Thomas M. Conte
2016	—	`conf`	Computationally-redundant energy-efficient processing for y'all (CREEPY). ICRC Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
2016	—	`conf`	Energy efficiency limits of logic and memory. ICRC Sapan Agarwal, Jeanine E. Cook, Erik DeBenedictis, Michael P. Frank, Gert Cauwenberghs, Sriseshan Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte
2016	—	`conf`	Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging. MEMSYS Rishiraj A. Bheda, Thomas M. Conte, Jeffrey S. Vetter
2015	J	`jnl`	Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs. ACM Trans. Archit. Code Optim. Brian P. Railing, Eric R. Hein, Thomas M. Conte
2015	A	`conf`	Rebooting Computing and Low-Power Image Recognition Challenge. ICCAD Yung-Hsiang Lu, Alan M. Kadin, Alexander C. Berg, Thomas M. Conte, Erik P. DeBenedictis, Rachit Garg, Ganesh Gingade, Bichlien Hoang, Yongzhen Huang, Boxun Li, Jingyu Liu, Wei Liu, Huizi Mao, Junran Peng, Tianqi Tang, Elie K. Track, Jingqiu Wang, Tao Wang, Yu Wang, Jun Yao
2015	J	`jnl`	Rebooting Computing: New Strategies for Technology Scaling. Computer Thomas M. Conte, Elie K. Track, Erik DeBenedictis
2015	J	`jnl`	The Computer Society Must Change. Computer Thomas M. Conte
2013	A*	`conf`	High-speed formal verification of heterogeneous coherence hierarchies. HPCA Jesse G. Beu, Jason A. Poovey, Eric R. Hein, Thomas M. Conte
2012	B	`conf`	Accelerating Multi-threaded Application Simulation through Barrier-Interval Time-Parallelism. MASCOTS Paul D. Bryan, Jason A. Poovey, Jesse G. Beu, Thomas M. Conte
2012	B	`conf`	Extrapolation Pitfalls When Evaluating Limited Endurance Memory. MASCOTS Rishiraj A. Bheda, Jesse G. Beu, Brian P. Railing, Thomas M. Conte
2011	—	`conf`	Energy efficient Phase Change Memory based main memory for future high performance systems. IGCC Rishiraj A. Bheda, Jason A. Poovey, Jesse G. Beu, Thomas M. Conte
2011	A*	`conf`	Manager-client pairing: a framework for implementing coherence hierarchies. MICRO Jesse G. Beu, Michel C. Rosier, Thomas M. Conte
2011	—	`conf`	Parallel Pattern Detection for Architectural Improvements. HotPar Jason A. Poovey, Brian P. Railing, Thomas M. Conte
2009	J	`jnl`	A Benchmark Characterization of the EEMBC Benchmark Suite. IEEE Micro Jason A. Poovey, Thomas M. Conte, Markus Levy, Shay Gal-On
2009	J	`jnl`	Embedded Multicore Processors and Systems. IEEE Micro Markus Levy, Thomas M. Conte
2009	A	`conf`	On power and energy trends of IEEE 802.11n PHY. MSWiM Balaji V. Iyer, Thomas M. Conte
2008	—	`conf`	A Power Model for Register-Sharing Structures. DIPES Balaji V. Iyer, Thomas M. Conte
2008	C	`conf`	Energy-aware opcode design. ICCD Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte
2007	C	`conf`	Combining cluster sampling with single pass methods for efficient sampling regimen design. ICCD Paul D. Bryan, Thomas M. Conte
2007	—	`conf`	Keynote: Insight, Not (Random) Numbers: An Embedded Perspective. HiPEAC Thomas M. Conte
2007	B	`conf`	Reverse State Reconstruction for Sampled Microarchitectural Simulation. ISPASS Paul D. Bryan, Michel C. Rosier, Thomas M. Conte
2005	J	`jnl`	Configurable string matching hardware for speeding up intrusion detection. SIGARCH Comput. Archit. News Monther Aldwairi, Thomas M. Conte, Paul D. Franzon
2005	J	`jnl`	Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. IEEE Trans. Computers Huiyang Zhou, Thomas M. Conte
2005	—	`ed.`	High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings HiPEAC Thomas M. Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer
2005	J	`jnl`	High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm. IEEE Trans. Parallel Distributed Syst. Emre Özer, Thomas M. Conte
2005	B	`conf`	Insight, not (random) numbers. ISPASS Thomas M. Conte
2005	Misc	`ed.`	Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005 CASES Thomas M. Conte, Paolo Faraboschi, William H. Mangione-Smith, Walid A. Najjar
2005	J	`jnl`	Spectral prefetcher: An effective mechanism for L2 cache prefetching. ACM Trans. Archit. Code Optim. Saurabh Sharma, Jesse G. Beu, Thomas M. Conte
2004	J	`jnl`	Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems. IEEE Micro Alessio Bechini, Thomas M. Conte, Cosimo Antonio Prete
2003	J	`jnl`	Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embed. Comput. Syst. Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
2003	A*	`conf`	Detecting Global Stride Locality in Value Streams. ISCA Huiyang Zhou, Jill Flanagan, Thomas M. Conte
2003	A	`conf`	Enhancing memory level parallelism via recovery-free value prediction. ICS Huiyang Zhou, Thomas M. Conte
2003	J	`jnl`	Modeling Value Speculation: An Optimal Edge Selection Problem. IEEE Trans. Computers Chao-ying Fu, Jill T. Bodine, Thomas M. Conte
2003	Misc	`ed.`	Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003 CASES Jaime H. Moreno, Praveen K. Murthy, Thomas M. Conte, Paolo Faraboschi
2002	J	`jnl`	Choosing the Brain(s) of an Embedded System. Computer Thomas M. Conte
2002	—	`conf`	Code Size Efficiency in Global Scheduling for ILP Processors. Interaction between Compilers and Computer Architectures Huiyang Zhou, Thomas M. Conte
2001	—	`conf`	Adaptive Mode Control: A Static-Power-Efficient Cache Design. IEEE PACT Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
2001	—	`conf`	Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. LCPC Huiyang Zhou, Matthew D. Jennings, Thomas M. Conte
2001	Misc	`conf`	Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. HiPC Emre Özer, Thomas M. Conte, Saurabh Sharma
2000	—	`conf`	A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization. IEEE PACT Kim M. Hazelwood, Thomas M. Conte
2000	J	`jnl`	Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. IEEE Trans. Computers Thomas M. Conte, Sumedh W. Sathaye
2000	J	`jnl`	System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. Very Large Scale Integr. Syst. Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen
1999	J	`jnl`	Challenges in processor modeling and validation [Guest Editors?? introduction]. IEEE Micro Pradip Bose, Thomas M. Conte, Todd M. Austin
1999	A*	`conf`	Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. MICRO Sergei Y. Larin, Thomas M. Conte
1999	A	`conf`	Dynamically Programmable Cache Evaluation and Virtualization. FPGA Mouna Nakkar, David G. Bentlage, John Harding, David Schwartz, Paul D. Franzon, Thomas M. Conte
1999	J	`jnl`	Editor's Introduction. Int. J. Parallel Program. Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman
1999	J	`jnl`	Editors' Introduction. Int. J. Parallel Program. Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman
1998	—	`conf`	A Fast Interrupt Handling Scheme for VLIW Processors. IEEE PACT Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte
1998	J	`jnl`	Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation. IEEE Trans. Computers Thomas M. Conte, Mary Ann Hirsch, Wen-mei W. Hwu
1998	J	`jnl`	MPS: Miss-Path Scheduling for Multiple-Issue Processors. IEEE Trans. Computers Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte
1998	J	`jnl`	Performance Analysis and Its Impact on Design. Computer Pradip Bose, Thomas M. Conte
1998	J	`jnl`	Subword extensions for video processing on mobile systems. IEEE Concurr. Matthew D. Jennings, Thomas M. Conte
1998	A*	`conf`	Treegion Scheduling for Wide Issue Processors. HPCA William A. Havanki, Sanjeev Banerjia, Thomas M. Conte
1998	A*	`conf`	Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. MICRO Emre Özer, Sanjeev Banerjia, Thomas M. Conte
1998	A*	`conf`	Value Speculation Scheduling for High Performance Processors. ASPLOS Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte
1997	J	`jnl`	Challenges to Combining General-Purpose and Multimedia Processors. Computer Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe
1997	—	`conf`	Combining General-Purpose and Multimedia in One Package: Challenges and Opportunities. HICSS (1) Thomas M. Conte, Andrew Wolfe
1997	J	`jnl`	Compilers for Instruction-Level Parallelism. Computer Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson
1997	J	`jnl`	Optimization of VLIW compatibility systems employing dynamic rescheduling. Int. J. Parallel Program. Thomas M. Conte, Sumedh W. Sathaye
1997	—	`conf`	Path Prediction for High Issue-Rate Processors. IEEE PACT Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte
1997	—	`conf`	Treegion Scheduling for Highly Parallel Processors. Euro-Par Sanjeev Banerjia, William A. Havanki, Thomas M. Conte
1996	A*	`conf`	A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. MICRO Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia
1996	A*	`conf`	Accurate and Practical Profile-driven Compilation Using the Profile Buffer. MICRO Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch
1996	Misc	`conf`	Bipartitioning for Hybrid FPGA-Software Simulatio. VLSI Design Ashutosh Singla, Thomas M. Conte
1996	J	`jnl`	Hardware-Based Profiling: An Effective Technique for Profile-Driven Optimization. Int. J. Parallel Program. Thomas M. Conte, Burzin A. Patel, Kishore N. Menezes, J. Stan Cox
1996	J	`jnl`	Importance of Profiling and Compatibility. ACM Comput. Surv. Thomas M. Conte
1996	A*	`conf`	Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. MICRO Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye
1996	C	`conf`	Reducing State Loss For Effective Trace Sampling of Superscalar Processors. ICCD Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes
1995	—	`conf`	A technique to determine power-efficient, high-performance superscalar processors. HICSS (1) Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye
1995	J	`jnl`	Advances in Benchmarking Techniques: New Standards and Quantitative Metrics. Adv. Comput. Thomas M. Conte, Wen-mei W. Hwu
1995	—	`conf`	Commercializing profile-driven optimization. HICSS (1) J. Stan Cox, David P. Howell, Thomas M. Conte
1995	A*	`conf`	Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. MICRO Thomas M. Conte, Sumedh W. Sathaye
1995	A*	`conf`	Optimization of Instruction Fetch Mechanisms for High Issue Rates. ISCA Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel
1994	—	`conf`	Fast Simulation of Computer Architectures: Introduction. HICSS (1) Thomas M. Conte, Charles E. Gimarc
1994	J	`jnl`	The Susceptibility of Programs to Context Switching. IEEE Trans. Computers Wen-mei W. Hwu, Thomas M. Conte
1994	A*	`conf`	Using branch handling hardware to support profile-driven optimization. MICRO Thomas M. Conte, Burzin A. Patel, J. Stan Cox
1993	C	`conf`	Determining Cost-Effective Multiple Issue Processor Designs. ICCD Thomas M. Conte, William H. Mangione-Smith
1993	J	`jnl`	The Effect of Code Expanding Optimizations on Instruction Cache Design. IEEE Trans. Computers William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu
1992	—	`—`	Systematic Computer Architecture Prototyping Thomas M. Conte
1992	C	`conf`	Systematic prototyping of superscalar computer architectures. RSP Thomas M. Conte, Wen-mei W. Hwu
1992	A*	`conf`	Tradeoffs in processor/memory interfaces for superscalar processors. MICRO Thomas M. Conte
1991	J	`jnl`	A brief survey of benchmark usage in the architecture community. SIGARCH Comput. Archit. News Thomas M. Conte, Wen-mei W. Hwu
1991	J	`jnl`	Benchmark Characterization. Computer Thomas M. Conte, Wen-mei W. Hwu
1989	A*	`conf`	A Simulation Study of Simultaneous Vector Prefetch Performance in Multiprocessor Memory Subsystems (Extended Abstract). SIGMETRICS Wen-mei W. Hwu, Thomas M. Conte
1989	A*	`conf`	Comparing Software and Hardware Schemes For Reducing the Cost of Branches. ISCA Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang
1984	J	`jnl`	Thinwire protocol for connecting personal computers to the Internet. RFC David J. Farber, Gary S. Delp, Thomas M. Conte